公开(公告)号：US20120112260A1

公开(公告)日：2012-05-10

申请号：US13291519

申请日：2011-11-08

申请人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

发明人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

IPC分类号： H01L29/788 ,  H01L29/78

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体器件。 该器件包括堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案包括邻近至少一个导电图案设置的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20110233648A1

公开(公告)日：2011-09-29

申请号：US13072078

申请日：2011-03-25

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

摘要翻译： 三维半导体存储器件及其制造方法。 三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一 垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。

公开(公告)号：US09917094B2

公开(公告)日：2018-03-13

申请号：US14920223

申请日：2015-10-22

申请人： Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

发明人： Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

IPC分类号： G11C5/06 ,  H01L27/11565 ,  G11C7/00 ,  H01L23/48 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/02

CPC分类号： H01L27/11565 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C7/18 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

公开(公告)号：US09443863B2

公开(公告)日：2016-09-13

申请号：US14819841

申请日：2015-08-06

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L23/535 ,  H01L29/78 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US09177613B2

公开(公告)日：2015-11-03

申请号：US14018885

申请日：2013-09-05

申请人： Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

发明人： Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  G11C7/18 ,  H01L27/115 ,  H01L27/02

CPC分类号： H01L27/11565 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C7/18 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

摘要翻译： 提供了一种半导体器件，其包括设置在基板上的栅极结构，插入在栅极结构之间的分离绝缘层以及通过每个栅极结构连接到基板的多个单元柱。 每个栅极结构可以包括垂直堆叠在基板上的水平电极，并且相邻的单元柱之间的间隔是不均匀的。

公开(公告)号：US09129950B2

公开(公告)日：2015-09-08

申请号：US14568737

申请日：2014-12-12

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US08952448B2

公开(公告)日：2015-02-10

申请号：US13828557

申请日：2013-03-14

申请人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

发明人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L27/115

CPC分类号： H01L27/088 ,  H01L27/11556 ,  H01L27/11578

摘要： A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P-N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type.

摘要翻译： 三维（3D）非易失性存储器件包括在其中具有第一导电类型区域的衬底上的非易失性存储器单元的垂直堆叠。 在基板中设置第二导电类型的掺杂区域。 该掺杂剂区域与第一导电类型的区域形成P-N整流结，并且具有相对于垂直堆叠的非易失性存储单元延伸的衬底的上表面凹陷的凹上表面。 提供电绝缘电极分离图案，其延伸穿过垂直堆叠的非易失性存储单元并进入第二导电类型的掺杂区域中的凹槽中。

公开(公告)号：US08450176B2

公开(公告)日：2013-05-28

申请号：US12968595

申请日：2010-12-15

申请人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

发明人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

IPC分类号： H01L21/336

CPC分类号： H01L21/28 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.

摘要翻译： 形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。 这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面 其中的陷阱密度。 该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。 也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

公开(公告)号：US08445317B2

公开(公告)日：2013-05-21

申请号：US13030454

申请日：2011-02-18

申请人： Jin Ha Jeong ,  Jung-Ho Kim ,  Kihyun Hwang ,  Yong-Hoon Son

发明人： Jin Ha Jeong ,  Jung-Ho Kim ,  Kihyun Hwang ,  Yong-Hoon Son

IPC分类号： H01L21/84

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

摘要： Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.

摘要翻译： 提供了制造半导体器件的方法。 在这些方法中，第一材料层和第二材料层可以交替地和重复堆叠在基底上。 可以形成贯穿第一材料层和第二材料层的开口。 可以通过使用旋涂工艺在开口中形成半导体溶液。

公开(公告)号：US08377817B2

公开(公告)日：2013-02-19

申请号：US13173304

申请日：2011-06-30

申请人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

发明人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC分类号： H01L21/4763

CPC分类号： H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.