公开(公告)号：US11749666B2

公开(公告)日：2023-09-05

申请号：US17068234

申请日：2020-10-12

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li

IPC: H01L25/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L25/0657 ,  H01L23/3121 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16251

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.

公开(公告)号：US20230178488A1

公开(公告)日：2023-06-08

申请号：US17643061

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Xiao Li ,  Jivaan Kishore Jhothiraman ,  Mohadeseh Asadolahi Baboli

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/11556

Abstract: A microelectronic device comprises stack structure comprising an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks comprises a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure comprises staircase structures each having steps comprising edges of the tiers of the stack structure. The filled trench comprises a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures comprise first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions than the first protrusions. Memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230164991A1

公开(公告)日：2023-05-25

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02 ,  H10B43/27 ,  H10B43/30

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/30625 ,  G11C16/0408 ,  G11C16/0466 ,  G11C5/025 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230164985A1

公开(公告)日：2023-05-25

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US20220310642A1

公开(公告)日：2022-09-29

申请号：US17211580

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11573

Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

公开(公告)号：US20210125899A1

公开(公告)日：2021-04-29

申请号：US17140610

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/427 ,  H01L25/065 ,  H01L23/46 ,  H01L23/473 ,  H01L23/42 ,  H01L23/433

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

公开(公告)号：US10952333B2

公开(公告)日：2021-03-16

申请号：US16707712

申请日：2019-12-09

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Xiao Li

IPC: H05K3/46 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/528 ,  H01L21/683 ,  H01L23/552 ,  H01L23/31

Abstract: Semiconductor devices, semiconductor device assemblies, and methods of making such semiconductor devices and semiconductor device assemblies. Material may be removed from a semiconductor device having a first thickness to obtain a second thickness and a carrier may be attached to the semiconductor device having a third thickness with the third thickness plus the second thickness substantially equaling the first thickness. The carrier has a coefficient of thermal expansion (CTE) that differs from the CTE of the semiconductor device. The addition of the carrier to the semiconductor device may change the overall warpage or CTE of a semiconductor device assembly. The semiconductor device assembly be include a redistribution layer between the semiconductor device and a substrate. A material may encapsulate the carrier and the semiconductor device. The carrier may provide electromagnetic shielding. A coating may be applied to external surface of the semiconductor device assembly to provide electromagnetic shielding.

公开(公告)号：US10861765B2

公开(公告)日：2020-12-08

申请号：US16431988

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： James M. Derderian ,  Andrew M. Bayless ,  Xiao Li

IPC: H01L23/367 ,  H01L23/532 ,  H01L23/498 ,  H01L21/683 ,  B32B43/00 ,  B32B7/12

Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.

公开(公告)号：US10548230B2

公开(公告)日：2020-01-28

申请号：US15862445

申请日：2018-01-04

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Xiao Li

IPC: H01L23/00 ,  H05K3/46 ,  H01L21/48 ,  H01L25/065 ,  H01L23/528 ,  H01L21/683

Abstract: Semiconductor devices, semiconductor device assemblies, and methods of making such semiconductor devices and semiconductor device assemblies. Material may be removed from a semiconductor device having a first thickness to obtain a second thickness and a carrier may be attached to the semiconductor device having a third thickness with the third thickness plus the second thickness substantially equaling the first thickness. The carrier has a coefficient of thermal expansion (CTE) that differs from the CTE of the semiconductor device. The addition of the carrier to the semiconductor device may change the overall warpage or CTE of a semiconductor device assembly. The semiconductor device assembly be include a redistribution layer between the semiconductor device and a substrate. A material may encapsulate the carrier and the semiconductor device. The carrier may provide electromagnetic shielding. A coating may be applied to external surface of the semiconductor device assembly to provide electromagnetic shielding.

公开(公告)号：US10461061B2

公开(公告)日：2019-10-29

申请号：US16272190

申请日：2019-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Anilkumar Chandolu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/367

Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.