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    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES
    41.
    发明申请
    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES 审中-公开

    公开(公告)号：US20190067247A1

    公开(公告)日：2019-02-28

    申请号：US15686024

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

    Semiconductor device structures and printed circuit boards comprising semiconductor devices
    44.
    发明授权
    Semiconductor device structures and printed circuit boards comprising semiconductor devices 有权
    包括半导体器件的半导体器件结构和印刷电路板

    公开(公告)号：US08736028B2

    公开(公告)日：2014-05-27

    申请号：US13848914

    申请日：2013-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Mark E. Tuttle

    IPC: H01L29/40

    CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K7/06 ,  H01L2924/014 ,  H01L2224/05552

    Abstract: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

    Abstract translation: 本发明涉及在半导体衬底中形成贯穿晶片互连的方法以及所得到的结构。 在一个实施例中，用于形成贯通晶片互连的方法包括提供在其表面上具有焊盘的衬底，在焊盘和衬底的表面上沉积钝化层，以及通过钝化层和焊盘形成孔 使用基本上连续的过程。 绝缘层沉积在孔中，随后是导电层和导电填料。 在本发明的另一实施例中，形成半导体器件，其包括延伸穿过导电焊盘并与导电焊盘电耦合的第一互连结构，而第二互连结构通过另一个导电焊盘形成，同时与之电绝缘。 还公开了使用该方法制造的半导体器件和组件。

    Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same
    45.
    发明授权
    Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same 有权

    公开(公告)号：US12218101B2

    公开(公告)日：2025-02-04

    申请号：US17697141

    申请日：2022-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

    Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

    Methods and systems for manufacturing semiconductor devices
    46.
    发明授权
    Methods and systems for manufacturing semiconductor devices 有权

    公开(公告)号：US12080678B2

    公开(公告)日：2024-09-03

    申请号：US17881572

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

    IPC: H01L23/00 ,  H01L23/48

    CPC classification number: H01L24/75 ,  H01L23/481 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/75317 ,  H01L2224/81203 ,  H01L2224/95091

    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

    Methods and systems for manufacturing semiconductor devices
    48.
    发明授权
    Methods and systems for manufacturing semiconductor devices 有权

    公开(公告)号：US11410963B2

    公开(公告)日：2022-08-09

    申请号：US17099655

    申请日：2020-11-16

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

    IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48

    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

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