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公开(公告)号：US11868639B2
公开(公告)日：2024-01-09
申请号：US17350866
申请日：2021-06-17
发明人： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
CPC分类号： G06F3/0647 , G06F3/0619 , G06F3/0673 , G06F11/1068 , G06F11/1402 , G11C29/52
摘要： At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
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公开(公告)号：US20230393736A1
公开(公告)日：2023-12-07
申请号：US17830166
申请日：2022-06-01
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Patrick R. Khayat , James Fitzpatrick , Kishore Kumar Muchherla , Sivagnanam Parthasarathy , Ashutosh Malshe
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/0679 , G06F3/0655
摘要： One of a plurality of compaction strategies to be performed on the memory device based on at least one characteristic of a memory device is identified. Each of the plurality of compaction strategies is to program host data from at least one single-level cell (SLC) of the memory device to at least one quad-level cell (QLC) of the memory device. One or more host data from a host system is received. A compaction operation on the one or more host data using the one of the plurality of compaction strategies is performed.
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公开(公告)号：US11829290B2
公开(公告)日：2023-11-28
申请号：US17247805
申请日：2020-12-23
CPC分类号： G06F12/0253 , G06F2212/1044
摘要： A processing device in a memory system determines a rate at which an amount of valid data is decreasing on a first block of the memory device and determines whether the rate at which the amount of valid data is decreasing on the first block satisfies a threshold criterion. Responsive to the rate at which the amount of valid data is decreasing on the first block satisfying the threshold criterion, the processing device performs a media management operation on the first block of the memory device.
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公开(公告)号：US11810627B2
公开(公告)日：2023-11-07
申请号：US17886884
申请日：2022-08-12
发明人： Kishore Kumar Muchherla , Harish R. Singidi , Renato C. Padilla , Vamsi Pavan Rayaprolu , Ashutosh Malshe , Sampath K. Ratnam
CPC分类号： G11C16/3431 , G06F11/076 , G06F11/3037 , G11C16/08 , G11C16/349 , G11C16/3427
摘要： A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.
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公开(公告)号：US11755472B2
公开(公告)日：2023-09-12
申请号：US17375478
申请日：2021-07-14
发明人： Kishore Kumar Muchherla , Peter Sean Feeley , Sampath K. Ratnam , Ashutosh Malshe , Christopher S. Hale
IPC分类号： G06F12/128 , G06F12/02 , G06F12/0897
CPC分类号： G06F12/0253 , G06F12/0246 , G06F12/0897 , G06F12/128
摘要： A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.
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公开(公告)号：US11721404B2
公开(公告)日：2023-08-08
申请号：US17484777
申请日：2021-09-24
发明人： Kishore K. Muchherla , Ashutosh Malshe , Preston A. Thomson , Michael G. Miller , Gary F. Besinga , Scott A. Stoller , Sampath K. Ratnam , Renato C. Padilla , Peter Feeley
CPC分类号： G11C16/349 , G11C16/12 , G11C2211/5641
摘要： Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
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公开(公告)号：US11720286B2
公开(公告)日：2023-08-08
申请号：US17516009
申请日：2021-11-01
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0653 , G06F3/0679
摘要： An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
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公开(公告)号：US11715541B2
公开(公告)日：2023-08-01
申请号：US17867538
申请日：2022-07-18
发明人： Renato C. Padilla , Sampath K. Ratnam , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Gary F. Besinga , Michael G. Miller , Tawalin Opastrakoon
CPC分类号： G11C29/10 , G06F11/076 , G06F11/0736 , G06F11/0757 , G06F11/1048 , G11C29/52
摘要： A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.
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公开(公告)号：US11714710B2
公开(公告)日：2023-08-01
申请号：US17544772
申请日：2021-12-07
发明人： Mustafa N. Kaynak , Larry J. Koudele , Michael Sheperek , Patrick R. Khayat , Sampath K. Ratnam
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C29/52
摘要： A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.
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公开(公告)号：US11709727B2
公开(公告)日：2023-07-25
申请号：US17216901
申请日：2021-03-30
发明人： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
CPC分类号： G06F11/0793 , G06F11/0727 , G06F11/0751
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.
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