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41.发明申请Integrated Circuit Structures Comprising Conductive Vias And Methods Of Forming Conductive Vias 有权包括导电通孔的集成电路结构和形成导电通孔的方法公开(公告)号：US20170062338A1
公开(公告)日：2017-03-02
申请号：US14838738
申请日：2015-08-28
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu
IPC: H01L23/528 , H01L23/522 , H01L27/24 , H01L21/768
CPC classification number: H01L23/5283 , H01L21/76816 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L27/11582 , H01L27/2463 , H01L28/00
Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.
Abstract translation: 形成导电通孔的方法包括在衬底内形成第一通孔和第二通孔。 第一导电性的第一导电材料形成为第一和第二通孔。 所述第一导电材料线路侧壁和所述第二通孔开口的基部以不足以填充所述第二通孔开口。 第二导电材料在第二通孔开口中形成在第一导电材料上的第二通孔开口中。 第二导电材料具有大于第一导电性的第二导电性。 第一通孔开口内的所有导电材料形成第一导电通孔，其通过第一导电通孔垂直地限定第一最大电导，并且第二通路孔内的所有导电材料形成第二导电通路，第二导电通路限定第二最大电导通过第二导电通孔， 大于所述第一最大电导。 公开了包含与制造方法无关的导电通孔的集成电路结构。
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42.发明申请公开(公告)号：US20160276409A1
公开(公告)日：2016-09-22
申请号：US15171890
申请日：2016-06-02
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall , Mike Violette
CPC classification number: H01L27/2436 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0002 , G11C13/0021 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/222 , H01L27/228 , H01L27/24 , H01L27/2463 , H01L43/08 , H01L43/10 , H01L45/065 , H01L45/085 , H01L45/141 , H01L45/146 , H01L45/147
Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.
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公开(公告)号：US09214386B2
公开(公告)日：2015-12-15
申请号：US14788960
申请日：2015-07-01
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu
IPC: H01L29/40 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528
CPC classification number: H01L21/76834 , H01L21/76802 , H01L21/76831 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53257 , H01L23/53271 , H01L27/101 , H01L2924/0002 , H01L2924/00
Abstract: Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A conductive plug is formed within a bottom region of the opening. A spacer is formed to line a lateral periphery of an upper region of the opening, and to leave an inner portion of an upper surface of the plug exposed. A conductive material is formed against the inner portion of the upper surface of the plug. Some embodiments include semiconductor constructions having a conductive plug within an insulative stack and against a copper-containing material. A spacer is over an outer portion of an upper surface of the plug and not directly above an inner portion of the upper surface. A conductive material is over the inner portion of the upper surface of the plug and against an inner lateral surface of the spacer.
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公开(公告)号：US20150279460A1
公开(公告)日：2015-10-01
申请号：US14739798
申请日：2015-06-15
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C8/08 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0033 , G11C13/0038 , G11C2013/0054 , G11C2013/0057 , G11C2013/0083 , G11C2213/77
Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.
Abstract translation: 本文描述的设备和方法可以操作以测量所选择的接入线路和与存储器阵列的多个存储器单元的选定单元相关联的选择的感测线之间的电压差。 可以将电压差与为存储器操作指定的参考电压进行比较。 可以响应于比较来调整施加到用于存储器操作的所选单元的选择电压，例如动态地补偿寄生电压降。
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公开(公告)号：US20210335420A1
公开(公告)日：2021-10-28
申请号：US17316271
申请日：2021-05-10
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall
Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.
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Patent Agency Ranking
公开(公告)号：US10679696B2
公开(公告)日：2020-06-09
申请号：US15620415
申请日：2017-06-12
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall
Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.
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公开(公告)号：US10650891B2
公开(公告)日：2020-05-12
申请号：US16419895
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
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公开(公告)号：US20190341122A1
公开(公告)日：2019-11-07
申请号：US16419885
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.
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公开(公告)号：US10381101B2
公开(公告)日：2019-08-13
申请号：US15849262
申请日：2017-12-20
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.
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公开(公告)号：US20190189209A1
公开(公告)日：2019-06-20
申请号：US15918662
申请日：2018-03-12
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
CPC classification number: G11C13/048 , G11C7/005 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C29/02 , G11C29/025 , G11C29/50004 , G11C29/56008 , G11C29/56016 , G11C2029/5602 , G11C2213/76
Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
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