公开(公告)号：US20070003873A1

公开(公告)日：2007-01-04

申请号：US11216084

申请日：2005-09-01

申请人： Shin-Shin Wang ,  Jong-Lieh Yang ,  Chii-Chang Lai ,  Hui-Ping Tsai ,  Wen-Ping Chu ,  Chien-Wen Chen ,  Chien-Liang Huang ,  Wen-Yih Liao ,  Ming-Chia Lee

发明人： Shin-Shin Wang ,  Jong-Lieh Yang ,  Chii-Chang Lai ,  Hui-Ping Tsai ,  Wen-Ping Chu ,  Chien-Wen Chen ,  Chien-Liang Huang ,  Wen-Yih Liao ,  Ming-Chia Lee

IPC分类号： G11B7/24 ,  C07D417/02 ,  C07D403/02 ,  C07F15/06

CPC分类号： C07D209/60 ,  C07D209/14 ,  C07D471/06 ,  G11B7/00455 ,  G11B7/244 ,  G11B7/246 ,  G11B7/2467 ,  G11B7/2472 ,  G11B7/2492 ,  G11B7/2495 ,  G11B7/2534 ,  G11B7/2542 ,  G11B7/2585 ,  G11B2007/24612 ,  Y10S430/146

摘要： A bis(indolestyryl) compound. The bis(indolestyryl) compound has formula (I): wherein A and B comprise benzene, naphthalene, or heterocyclic ring containing O, S, or N, R1 and R1′ are H, halogen atoms, C1-5 alkyl, nitro, ester, carboxyl, sulfo, sulfonamide, amide, sulfo ester, C1-3 alkoxy, amino, alkylamino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, R2, R2′, R3, and R3′ comprise H, C1-6 alkyl, C6-18 aryl, C2-6 alkenyl, C3-6 cycloalkenyl, or C3-6 cycloalkyl, R4 is H, C1-5 alkyl, hydroxyl, halogen atoms, or alkoxy, R5 and R5′ comprise H, halogen atoms, C1-5 alkyl, nitro, C1-3 alkoxy, amino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, W comprises oxygen, sulfur, selenium, —NR, or —C(CH3)2, n is 1˜18, and Z1 and Z2 are different and comprise an anion or an anionic organometallic complex with +1 or +2 valence, wherein R bonded to nitrogen is C1-4 alkyl.

摘要翻译： 双（吲哚美辛）化合物。 双（吲哚美辛）化合物具有式（I）：其中A和B包含含有O，S或N的苯，萘或杂环，R 1和R 1'是H，卤素原子，C 1-5 - 烷基，硝基，酯，羧基，磺基，磺酰胺，酰胺，磺基酯，C 1-3烷氧基，氨基，烷基氨基，氰基，C 1-6 烷基磺酰基或C 2-7烷氧基羰基，R 2，R 2，R 3和R 3 N 3'包括H，C 1-6烷基，C 6-18芳基，C 2-6链烯基 ，C 3-6环烯基或C 3-6环烷基，R 4是H，C 1-5 - 烷基，羟基，卤原子或烷氧基，R 5和R 5包括H，卤素原子，C 1-5烷基， 硝基，C 1-3烷氧基，氨基，氰基，C 1-6烷基磺酰基或C 2-7烷氧基羰基，W包括氧 ，硫，硒，-NR或-C（CH 3）2，n为1〜18，Z 1，Z 2， SUB> 2 不同 d包含具有+1或+2价的阴离子或阴离子有机金属络合物，其中与氮键合的R为C 1-4烷基。

公开(公告)号：US08959234B2

公开(公告)日：2015-02-17

申请号：US13087378

申请日：2011-04-15

申请人： Po-Yen Lee ,  Chien-Wen Chen ,  Pai-Chang Yeh ,  Li-Wen Lian

发明人： Po-Yen Lee ,  Chien-Wen Chen ,  Pai-Chang Yeh ,  Li-Wen Lian

IPC分类号： G06F15/16 ,  G06F21/41 ,  H04W56/00 ,  H04W76/02 ,  H04L29/06 ,  H04L29/08 ,  G06Q10/10 ,  H04W12/06

CPC分类号： G06F21/41 ,  G06Q10/10 ,  H04L63/0815 ,  H04L67/02 ,  H04L67/125 ,  H04L69/14 ,  H04W12/06 ,  H04W56/001 ,  H04W76/15

摘要： A method and a system for providing online services corresponding to multiple mobile devices, a server, a mobile device, and a computer program product are provided. The server provides a service website. In the present method, a login request of a user account of the service website is received from a terminal device. A first connection with a first mobile device of the user account is established, and a first device data of the first mobile device is obtained. A second connection with a second mobile device of the user account is established while maintaining the first connection, and a second device data of the second mobile device is obtained. A first online service corresponding to the first mobile device and a second online service corresponding to the second mobile device are provided on the service website according to the first device data and the second device data.

摘要翻译： 提供了一种用于提供与多个移动设备，服务器，移动设备和计算机程序产品相对应的在线服务的方法和系统。 服务器提供服务网站。 在本方法中，从终端装置接收到服务网站的用户账号的登录请求。 建立与用户帐户的第一移动设备的第一连接，并获得第一移动设备的第一设备数据。 在保持第一连接的同时建立与用户帐户的第二移动设备的第二连接，并且获得第二移动设备的第二设备数据。 根据第一设备数据和第二设备数据，在服务网站上提供对应于第一移动设备的第一在线服务和对应于第二移动设备的第二在线服务。

公开(公告)号：US08621571B2

公开(公告)日：2013-12-31

申请号：US13039260

申请日：2011-03-02

申请人： Po-Yen Lee ,  Chien-Wen Chen ,  Pai-Chang Yeh ,  Li-Wen Lian

发明人： Po-Yen Lee ,  Chien-Wen Chen ,  Pai-Chang Yeh ,  Li-Wen Lian

IPC分类号： G06F21/00

CPC分类号： H04L63/08 ,  H04L67/303 ,  H04W12/06

摘要： An online service providing system, a method, a server, and a mobile device thereof, and a computer program product are provided. The method includes sending a verification link corresponding to a user account that is not verified; after receiving a verification request corresponding to the verification link, determining whether a device identification sent by the mobile device that has logged in the user account is received; when receiving the device identification, confirming whether the user account is verified according to the device identification; after confirming that the user account is verified, when receiving a service request sent by a terminal device logging the user account into a service website, determining a homepage of the service website according to the device identification, and providing the online service corresponding to the mobile device to the terminal device through the service website.

摘要翻译： 提供在线服务提供系统，方法，服务器及其移动设备以及计算机程序产品。 该方法包括发送对应于未被验证的用户帐户的验证链接; 在接收到与所述验证链接相对应的验证请求之后，确定是否接收到由所述移动设备发送的登录了所述用户帐户的设备标识; 当接收到设备标识时，根据设备标识确认用户帐号是否被验证; 在确认用户帐户被验证之后，当接收到终端设备发送的登录用户账户到服务网站的服务请求时，根据设备标识来确定服务网站的主页，并提供对应于移动设备的在线服务 设备通过服务网站到终端设备。

公开(公告)号：US08621406B2

公开(公告)日：2013-12-31

申请号：US13416642

申请日：2012-03-09

申请人： Cheok-Kei Lei ,  Yi-Tang Lin ,  Hsiao-Hui Chen ,  Yu-Ning Chang ,  Shu-Yu Chen ,  Chien-Wen Chen ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

发明人： Cheok-Kei Lei ,  Yi-Tang Lin ,  Hsiao-Hui Chen ,  Yu-Ning Chang ,  Shu-Yu Chen ,  Chien-Wen Chen ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/823821

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局并生成相应的FinFET结构。

公开(公告)号：US08572537B2

公开(公告)日：2013-10-29

申请号：US13527096

申请日：2012-06-19

申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan-Sin Chang ,  Chien-Wen Chen

发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan-Sin Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

公开(公告)号：US08492883B2

公开(公告)日：2013-07-23

申请号：US12192702

申请日：2008-08-15

申请人： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Chien-Wen Chen ,  Hsu-Yang Lee

发明人： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Chien-Wen Chen ,  Hsu-Yang Lee

IPC分类号： H01L23/495

CPC分类号： H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.

摘要翻译： 描述半导体封装和相关方法。 在一个实施例中，封装包括管芯焊盘，多个引线，芯片和封装体。 所述管芯焊盘包括：（1）外围边缘区域，其限定具有包括中心部分的空腔底部的空腔; （2）上倾斜部分; 和（3）下倾斜部分。 每个引线包括上倾斜部分和下倾斜部分。 芯片设置在空腔底部的中心部分并且连接到引线。 封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。 芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。

公开(公告)号：US08444705B2

公开(公告)日：2013-05-21

申请号：US13308014

申请日：2011-11-30

申请人： Chien-Wen Chen ,  Chien-Cheng Chen

发明人： Chien-Wen Chen ,  Chien-Cheng Chen

IPC分类号： A61F2/48

CPC分类号： A61F2/644 ,  A61F2/76 ,  A61F2002/5006 ,  A61F2002/5007 ,  A61F2002/5021 ,  A61F2002/5033 ,  A61F2002/5043 ,  A61F2002/5073

摘要： A knee joint prosthesis is adapted for interconnecting a prosthetic lower leg and a prosthetic thigh. The knee joint prosthesis includes a knee seat disposed under and connected to the prosthetic thigh, a connecting seat disposed above and connected to the prosthetic lower leg, a link assembly, and an adjusting unit. The link assembly includes a plurality of links each connected pivotally to the knee seat and the connecting seat in such a manner to allow the knee joint prosthesis to change between an elevated position and a flexed position. The adjusting unit is disposed in the knee seat, and is operable to cooperate with the link assembly to adjust difficulty level of changing the knee joint prosthesis between the elevated and flexed positions.

摘要翻译： 膝关节假体适于将假肢小腿和假腿大腿相互连接。 膝关节假体包括设置在假体大腿下方并连接到假体大腿的膝盖座，设置在假肢小腿上方并连接到假肢小腿的连接座，连杆组件和调节单元。 连杆组件包括多个连接件，每个连接件以这样的方式枢转地连接到膝盖座和连接座，以允许膝关节假体在升高位置和弯曲位置之间改变。 调节单元设置在膝盖座中，并且可操作以与连杆组件协作，以调节在升高位置和弯曲位置之间改变膝关节假体的难度水平。

公开(公告)号：US08397380B2

公开(公告)日：2013-03-19

申请号：US12730857

申请日：2010-03-24

申请人： Chia-Jen Kao ,  Chen-Fa Tsai ,  Chien-Wen Chen

发明人： Chia-Jen Kao ,  Chen-Fa Tsai ,  Chien-Wen Chen

IPC分类号： H05K3/34

CPC分类号： H01L21/563 ,  H01L23/49816 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.

摘要翻译： 制造集成电路封装的方法包括：在BGA模块的一侧提供包括BGA球的球栅阵列（BGA）模块; 提供基底; 并将BGA模块放置在基底基板上。 BGA球放置在BGA模块和基底之间。 粘合剂施加在BGA模块和基底基板之间并与之接触。 然后将粘合剂固化。 在固化粘合剂的步骤之后，BGA球再次流动。

公开(公告)号：US20120052603A1

公开(公告)日：2012-03-01

申请号：US13064161

申请日：2011-03-09

申请人： Chien-Wen Chen ,  Chia-Jen Kao ,  Jui-Cheng Chuang

发明人： Chien-Wen Chen ,  Chia-Jen Kao ,  Jui-Cheng Chuang

IPC分类号： H01L21/66

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L22/12 ,  H01L23/055 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

摘要翻译： 提供了一种用于检测倒装芯片球栅阵列封装结构的欠补充空隙的方法，其包括在其中提供具有互连结构的衬底和多个中介层; 提供具有活性表面和背面的芯片，以及在芯片的有源表面上的多个第一连接元件; 将所述芯片的有源表面安装并电连接在所述基板上; 执行至少一次IR回流以将所述多个第一连接元件固定在所述基板上; 填充封装材料以覆盖所述芯片的有效表面和所述多个第一连接元件; 执行检测处理以检测在所述芯片的有效表面和所述多个第一元件之间不形成所述空隙; 以及在所述基板的背面上形成多个第二连接元件以获得倒装芯片球栅阵列封装结构。

公开(公告)号：US08115285B2

公开(公告)日：2012-02-14

申请号：US12192805

申请日：2008-08-15

申请人： Chien-Wen Chen ,  Yi-Shao Lai ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Hsu-Yang Lee

发明人： Chien-Wen Chen ,  Yi-Shao Lai ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Hsu-Yang Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

摘要翻译： 描述半导体封装和相关方法。 在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。 管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。 每个引线包括上倾斜部分和下倾斜部分。 芯片设置在腔体底部并耦合到引线。 封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。 芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。 保护层基本上覆盖至少一个引线的下倾斜部分和下表面。