公开(公告)号：US06476653B1

公开(公告)日：2002-11-05

申请号：US09774172

申请日：2001-02-01

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： H03L706

CPC分类号： H03L7/0814

摘要： The present invention provides a DLL circuit performing a phase adjustment in accordance to an output load, and capable of adjusting the phase in a shot time. In the present invention, in a delayed lock loop (DLL) circuit that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, the operating delay time of an output buffer is measured and the timing of the control clock is adjusted in accordance with this operating delay time. As a result, the timing of the output clock of the first variable delay circuit delay circuit is adjusted in accordance with the magnitude of the external load. This output clock or the output clock of a separate variable delay circuit subject to the same delay control is then utilized as a control clock.

摘要翻译： 本发明提供一种根据输出负载执行相位调整并且能够在拍摄时间内调节相位的DLL电路。 在本发明中，在延迟锁定环（DLL）电路中，通过延迟参考时钟产生与参考时钟具有规定相位关系的控制时钟，测量输出缓冲器的操作延迟时间，并且控制定时 时钟根据该操作延迟时间进行调整。 结果，根据外部负载的大小来调整第一可变延迟电路延迟电路的输出时钟的定时。 然后将该输出时钟或受到相同延迟控制的单独可变延迟电路的输出时钟用作控制时钟。

公开(公告)号：US06349068B2

公开(公告)日：2002-02-19

申请号：US09828847

申请日：2001-04-10

申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki

发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki

IPC分类号： G11C700

CPC分类号： G11C11/40622 ,  G11C11/406

摘要： A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.

摘要翻译： 刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。 第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。 通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。

公开(公告)号：US06333660B2

公开(公告)日：2001-12-25

申请号：US09780475

申请日：2001-02-12

申请人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

发明人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

IPC分类号： H03K3013

CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

公开(公告)号：US6154405A

公开(公告)日：2000-11-28

申请号：US924315

申请日：1997-09-05

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/1048 ,  G11C7/12

摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.

摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

公开(公告)号：US6151274A

公开(公告)日：2000-11-21

申请号：US440665

申请日：1999-11-16

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC分类号： H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

摘要翻译： 公开了一种用于实现这种系统的系统和半导体器件。 该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。 即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据 可以高速转移。 在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。 在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

公开(公告)号：US6028816A

公开(公告)日：2000-02-22

申请号：US924705

申请日：1997-09-05

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC分类号： H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

公开(公告)号：US07911825B2

公开(公告)日：2011-03-22

申请号：US11512319

申请日：2006-08-30

申请人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

发明人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

IPC分类号： G11C11/24

CPC分类号： G11C8/16 ,  G06F13/1605 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/24 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/409 ,  G11C11/4093 ,  G11C2207/107 ,  G11C2207/108

摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

摘要翻译： 半导体存储器件包括多个N个外部端口，每个N个外部端口接收命令;以及内部电路，其在输入到一个外部端口的命令的最小间隔期间执行至少N次访问操作。

公开(公告)号：US07391255B2

公开(公告)日：2008-06-24

申请号：US09874037

申请日：2001-06-06

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： H01L25/00

CPC分类号： G11C7/1057 ,  G06F1/10 ,  G06F5/06 ,  G11C5/063 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/081

摘要： A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

摘要翻译： 模块包括半导体器件，产生第二时钟的相位调整电路，使得从半导体器件输出的相位调整信号和第一时钟具有预定的相位关系，以及设置在半导体器件中的输出电路， 来自第二个时钟的相位调整信号。

公开(公告)号：US07317241B2

公开(公告)日：2008-01-08

申请号：US11143649

申请日：2005-06-03

申请人： Yasurou Matsuzaki ,  Yasuharu Sato ,  Tadao Aikawa ,  Masafumi Yamazaki ,  Takaaki Suzuki

发明人： Yasurou Matsuzaki ,  Yasuharu Sato ,  Tadao Aikawa ,  Masafumi Yamazaki ,  Takaaki Suzuki

IPC分类号： H01L23/58

CPC分类号： G11C5/06 ,  G11C5/00 ,  G11C5/04 ,  G11C5/063 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/105 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2924/13091 ,  H04L12/40 ,  H04L12/4625 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

公开(公告)号：US07304907B2

公开(公告)日：2007-12-04

申请号：US11790832

申请日：2007-04-27

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

摘要翻译： 根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令 在规定的刷新周期内部。 并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 根据本发明，当产生刷新定时信号时，可以在外部命令操作中中断刷新操作。