公开(公告)号：US20050170196A1

公开(公告)日：2005-08-04

申请号：US11046873

申请日：2005-02-01

申请人： Seok-Jun Won ,  Weon-Hong Kim ,  Min-Woo Song

发明人： Seok-Jun Won ,  Weon-Hong Kim ,  Min-Woo Song

IPC分类号： H01L21/02 ,  B08B7/00 ,  B08B9/00 ,  B32B3/00 ,  B32B15/00 ,  C23C16/44 ,  C23F4/00

CPC分类号： H01J37/32862 ,  B08B7/0035 ,  C23C16/4405 ,  C23F4/00 ,  Y10S134/902 ,  Y10S438/905 ,  Y10T428/12528 ,  Y10T428/24917 ,  Y10T428/31678

摘要： A method of cleaning a reaction chamber using a substrate having a metal catalyst thereon is disclosed. The method includes preparing a substrate having a catalyst layer to activate a cleaning gas. The substrate is introduced into the reaction chamber. Next, a cleaning gas is introduced into the reaction chamber. Contaminations in the reaction chamber are exhausted. The substrate having a metal catalyst layer is also disclosed.

摘要翻译： 公开了一种使用其上具有金属催化剂的基板清洁反应室的方法。 该方法包括制备具有催化剂层以激活清洁气体的基材。 将基底引入反应室。 接下来，将清洁气体引入反应室。 反应室内的污染已经耗尽。 还公开了具有金属催化剂层的基板。

公开(公告)号：US08389355B2

公开(公告)日：2013-03-05

申请号：US12984823

申请日：2011-01-05

申请人： Seok-Jun Won ,  Jung-Min Park

发明人： Seok-Jun Won ,  Jung-Min Park

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L28/60

摘要： In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.

摘要翻译： 在半导体集成电路器件及其形成方法中，半导体器件包括：半导体衬底; 绝缘体，位于衬底的顶部，限定绝缘体区域; 在基板上的导电层图案，所述导电层图案从公共导电层图案化，所述导电层图案包括位于绝缘体区域中的绝缘体上的第一图案部分和位于所述绝缘体区域的有源区域中的第二图案部分 衬底，其中所述第二图案部分包括所述有源区中的晶体管的栅极; 以及在所述绝缘体区域中的绝缘体上的电容器，所述电容器包括：在所述导电层图案的所述第一图案部分上的下电极，所述下电极上的电介质层图案，以及所述电介质层图案上的上电极。

公开(公告)号：US07833580B2

公开(公告)日：2010-11-16

申请号：US10859166

申请日：2004-06-03

申请人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

发明人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

IPC分类号： C23C18/00 ,  C23C16/26

CPC分类号： C23C16/4554 ,  C23C16/0281 ,  C23C16/26 ,  C30B29/02 ,  C30B29/605

摘要： A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.

摘要翻译： 形成碳纳米材料层的方法可以包括循环沉积技术。 在该方法中，可以在基板上形成化学吸附层或化学气相沉积层。 杂质可以从化学吸附层或化学气相沉积层去除，以在基底上形成碳原子层。 可以通过重复该方法形成多于一个的碳原子层。

公开(公告)号：US20070267705A1

公开(公告)日：2007-11-22

申请号：US11588575

申请日：2006-10-27

申请人： Seok-Jun Won ,  Jung-Min Park

发明人： Seok-Jun Won ,  Jung-Min Park

IPC分类号： H01L29/94 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L28/60

摘要： In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.

摘要翻译： 在半导体集成电路器件及其形成方法中，半导体器件包括：半导体衬底; 绝缘体，位于衬底的顶部，限定绝缘体区域; 在基板上的导电层图案，所述导电层图案从公共导电层图案化，所述导电层图案包括位于绝缘体区域中的绝缘体上的第一图案部分和位于所述绝缘体区域的有源区域中的第二图案部分 衬底，其中所述第二图案部分包括所述有源区中的晶体管的栅极; 以及在所述绝缘体区域中的绝缘体上的电容器，所述电容器包括：在所述导电层图案的所述第一图案部分上的下电极，所述下电极上的电介质层图案，以及所述电介质层图案上的上电极。

公开(公告)号：US07180117B2

公开(公告)日：2007-02-20

申请号：US10676865

申请日：2003-09-30

申请人： Seok-Jun Won

发明人： Seok-Jun Won

IPC分类号： H01L27/108

CPC分类号： H01L28/55 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31645 ,  H01L21/31691 ,  H01L21/3185 ,  H01L23/5223 ,  H01L28/65 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to the lower interconnection; a concave dielectric layer formed on the lower electrode; a concave upper electrode formed on the dielectric layer; a first upper interconnection that is electrically coupled to the lower interconnection; and a second upper interconnection that is coupled to the upper electrode. The concave upper electrode is larger than the lower electrode.

摘要翻译： 本发明的实施例提供了防止电介质层劣化的扁平型电容器，从而改善了电容器的电性能。 电容器包括形成在半导体衬底的预定部分中的下互连，形成在下互连上的下电极，电连接到下互连; 形成在下电极上的凹电介质层; 形成在电介质层上的凹上电极; 电耦合到所述下互连的第一上互连; 以及耦合到上电极的第二上互连。 凹状上部电极比下部电极大。

公开(公告)号：US07084056B2

公开(公告)日：2006-08-01

申请号：US10879076

申请日：2004-06-30

申请人： Seok-Jun Won

发明人： Seok-Jun Won

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L27/14636 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14601 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.

摘要翻译： 用于高度集成的半导体器件的电互连包括在衬底上具有至少第一凹部的第一绝缘层。 第一凹部被金属填充以形成第一金属图案。 在第一绝缘层和防止金属扩散的第一金属图案上设置包括高透光率的氧化铝的扩散阻挡层。 包括用于暴露第一金属图案的上表面的第二凹部的绝缘夹层设置在扩散阻挡层上。 第二凹部用金属填充以形成第二金属图案。 电互连可以与图像传感器一起使用。 金属可以是铜。 扩散阻挡层的高透光率确保外部光到达光电检测器。 扩散阻挡层的氧化铝减小电互连的寄生电容。

公开(公告)号：US07049648B2

公开(公告)日：2006-05-23

申请号：US10309547

申请日：2002-12-03

申请人： Seok-Jun Won ,  Cha-Young Yoo

发明人： Seok-Jun Won ,  Cha-Young Yoo

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L27/10855

摘要： The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.

公开(公告)号：US20050230729A1

公开(公告)日：2005-10-20

申请号：US11065988

申请日：2005-02-25

申请人： Seok-Jun Won

发明人： Seok-Jun Won

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/65 ,  H01L28/91

摘要： In a method of fabricating a capacitor, an interlayer insulating layer is formed on a semiconductor substrate. A contact plug penetrating the interlayer insulating layer is formed. An oxidation barrier layer and a molding layer are sequentially formed on the semiconductor substrate having the contact plug and the interlayer insulating layer. The molding layer is patterned to form a first lower electrode contact hole which exposes the oxidation barrier layer on the contact plug. An electrode layer pattern covering an inner sidewall of the first lower electrode contact hole is formed. The oxidation barrier layer exposed by the electrode layer pattern is etched to form a second lower electrode contact hole which exposes the contact plug. A conductive layer pattern covering an inner wall of the second lower electrode contact hole is then formed.

摘要翻译： 在制造电容器的方法中，在半导体衬底上形成层间绝缘层。 形成贯穿层间绝缘层的接触插塞。 在具有接触插塞和层间绝缘层的半导体衬底上依次形成氧化阻隔层和成型层。 模塑层被图案化以形成暴露接触插塞上的氧化阻挡层的第一下电极接触孔。 形成覆盖第一下电极接触孔的内侧壁的电极层图案。 蚀刻由电极层图案露出的氧化阻挡层，形成暴露接触插塞的第二下电极接触孔。 然后形成覆盖第二下电极接触孔的内壁的导电层图案。

公开(公告)号：US20050167722A1

公开(公告)日：2005-08-04

申请号：US11047817

申请日：2005-02-02

申请人： Seok-Jun Won

发明人： Seok-Jun Won

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/55 ,  H01L27/0805 ,  H01L27/0811

摘要： Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate positioned, an upper plate electrically connected to the lower plate and positioned above the lower plate, and an intermediate plate interposed between the lower plate and the upper plate. An upper interconnection line is positioned at the same level as the upper plate. The upper interconnection line is electrically connected to the intermediate plate. As a result, the upper plate may be formed by a damascene process.

摘要翻译： 公开了具有双层叠MIM电容器的半导体器件及其制造方法。 半导体器件包括形成在半导体衬底上的双层叠层MIM电容器。 双堆叠MIM电容器包括下板，下板，电连接到下板并位于下板上方的上板，以及插在下板和上板之间的中间板。 上部互连线定位在与上板相同的水平面上。 上互连线电连接到中间板。 结果，上板可以通过镶嵌工艺形成。

公开(公告)号：US09287181B2

公开(公告)日：2016-03-15

申请号：US14592842

申请日：2015-01-08

申请人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

发明人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽; 在第一沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后进行退火; 退火后，依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数调整层和栅极导体; 并在栅极导体上形成覆盖层。