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    System and method to defragment a memory
    41.
    发明授权
    System and method to defragment a memory 有权
    系统和方法来对内存进行碎片整理

    公开(公告)号：US09436606B2

    公开(公告)日：2016-09-06

    申请号：US14146576

    申请日：2014-01-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F12/08 ,  G06F12/10 ,  G06F3/06

    CPC classification number: G06F12/0833 ,  G06F3/0608 ,  G06F12/0873 ,  G06F12/0895 ,  G06F12/12 ,  G06F2206/1004 ,  Y02D10/13

    Abstract: A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

    Abstract translation: 公开了一种用于对存储器进行碎片整理的系统和方法。 在特定实施例中，一种方法包括将存储在存储器的第一物理存储器地址上的数据从存储器加载到数据高速缓存的高速缓存行中。 第一个物理内存地址映射到第一个虚拟内存地址。 该方法还包括在数据高速缓存处启动与第一虚拟存储器地址相关联的查找信息的修改，使得第一虚拟存储器地址对应于存储器的第二物理存储器地址。 该方法还包括在数据高速缓存处修改与高速缓存行相关联的信息，以指示高速缓存线对应于第二物理存储器地址而不是第一物理存储器地址。

    Integrated MRAM module
    42.
    发明授权
    Integrated MRAM module 有权
    集成MRAM模块

    公开(公告)号：US09378793B2

    公开(公告)日：2016-06-28

    申请号：US13721092

    申请日：2012-12-20

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Jungwon Suh

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/16 ,  G11C11/1653 ,  G11C2211/5643 ,  Y10T29/49117

    Abstract: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.

    Abstract translation: 用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。 集成电路包括处理器，其中没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或 多个包装。 第二包还包括存储器控制器逻辑。 简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主内存之间的积极预取，改进的页面处理和改进的密封能力。

    Cache structure with parity-protected clean data and ECC-protected dirty data
    43.
    发明授权
    Cache structure with parity-protected clean data and ECC-protected dirty data 有权
    具有奇偶校验保护的清除数据和ECC保护的脏数据的缓存结构

    公开(公告)号：US09250998B2

    公开(公告)日：2016-02-02

    申请号：US14090427

    申请日：2013-11-26

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F11/10 ,  G06F12/00

    CPC classification number: G06F11/1064 ,  G06F12/00

    Abstract: A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache.

    Abstract translation: 响应于确定数据是干净的，一种方法包括生成与要存储在高速缓存中的数据相关联的错误检测信息。 该方法还包括将清洁数据存储在高速缓存的第一区域。 响应于确定数据是脏的，该方法还包括生成与要存储在高速缓存中的数据相关联的纠错信息。 该方法还包括将脏数据存储在高速缓存的第二区域。

    System and method to dynamically determine a timing parameter of a memory device
    44.
    发明授权
    System and method to dynamically determine a timing parameter of a memory device 有权
    用于动态地确定存储器件的定时参数的系统和方法

    公开(公告)号：US09224442B2

    公开(公告)日：2015-12-29

    申请号：US13842410

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F12/00 ,  G11C7/22 ,  G06F3/06 ,  G11C11/4076 ,  G06F17/50 ,  G11C29/02 ,  G11C29/50 ,  G11C29/04

    CPC classification number: G11C7/22 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0629 ,  G06F12/00 ,  G06F17/5031 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/50012 ,  G11C2029/0409 ,  G11C2207/2254

    Abstract: A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter.

    Abstract translation: 一种特定的方法包括从处理器接收在存储器设备处的第一存储器访问请求。 该方法还包括基于存储器件的定时参数来处理第一存储器访问请求。 该方法还包括从处理器接收在存储器设备处的第二存储器访问请求。 该方法还包括基于由第一存储器访问请求和第二存储器访问请求识别的地址修改存储器件的定时参数以产生修改的定时参数。 该方法还包括基于修改的定时参数来处理第二存储器访问请求。

    RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE
    48.
    发明申请
    RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE 有权
    具有两个二极管访问器件的基于电阻的存储器

    公开(公告)号：US20140119097A1

    公开(公告)日：2014-05-01

    申请号：US14147817

    申请日：2014-01-06

    Applicant: QUALCOMM Incorporated

    Inventor： Wuyang Hao ,  Jungwon Suh ,  Kangho Lee ,  Taehyun Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74

    Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

    Abstract translation: 基于电阻的存储器包括二极管接入设备。 在特定实施例中，一种方法包括利用第一电​​压来偏置位线。 该方法还包括利用第二电压来偏置感测线。 偏置位线并偏置感测线通过电阻型存储元件并通过第一二极管和第二二极管之一产生电流。 第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

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