公开(公告)号：US20170280562A1

公开(公告)日：2017-09-28

申请号：US15079811

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/40 ,  H03H7/01 ,  H05K3/30

CPC classification number: H05K1/181 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/141 ,  H05K3/10 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/09227 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2201/10962 ,  H05K2201/2036

Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.

公开(公告)号：US20170098663A1

公开(公告)日：2017-04-06

申请号：US15380800

申请日：2016-12-15

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/768 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US09343403B2

公开(公告)日：2016-05-17

申请号：US14483944

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01L23/522 ,  H01L21/283 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L21/283 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L27/01 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.

Abstract translation: 集成电路器件包括衬底。 集成电路器件还包括第一导电叠层，其包括参考衬底的第一高度处的后端行（BEOL）导电层。 集成电路器件还包括第二导电叠层，其包括相对于衬底的第二高度处的BEOL导电层。 第二个高程与第一个高程不同。

公开(公告)号：US09275786B2

公开(公告)日：2016-03-01

申请号：US14335609

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01F5/00 ,  H01F27/28 ,  H01F27/29 ,  H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

Abstract translation: 三维（3D）正交电感器对被嵌入并由衬底支撑，并且具有第一电感器，其具有卷绕第一绕组轴线的第一线圈和具有卷绕第二绕组轴线的第二线圈的第二电感器 。 第二卷绕轴线与第一卷绕轴线正交。 第二绕组轴线在第一绕组轴线处于衬底内的交点处。

公开(公告)号：US20150303148A1

公开(公告)日：2015-10-22

申请号：US14254764

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Robert Paul Mikulka

IPC: H01L23/552 ,  H01L23/00 ,  H05K9/00 ,  H01L23/04 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/32 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01R12/7076 ,  H01R12/714 ,  H05K1/181 ,  H05K9/0032 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.

Abstract translation: 一些新颖特征涉及包括封装衬底，管芯，封装层和第一组金属层的集成器件封装（例如管芯封装）。 封装衬底包括第一表面和第二表面。 管芯耦合到封装衬底的第一表面。 封装层封装模具。 第一组金属层耦合到封装层的第一外表面。 在一些实施方案中，第一组金属层被配置为作为集成器件封装的管芯到线连接器工作。 在一些实施方案中，集成器件封装包括耦合到封装衬底的第二表面的第二组金属层。 在一些实施方案中，集成器件封装包括耦合到封装层的第二外表面的第二组金属层。

公开(公告)号：US10944379B2

公开(公告)日：2021-03-09

申请号：US15379392

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Changhan Hobie Yun ,  Shiqun Gu ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim

IPC: H03H9/05 ,  H03H9/64 ,  H03H3/08 ,  H03H9/72 ,  H03H9/70 ,  H03H3/02

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

公开(公告)号：US10607980B2

公开(公告)日：2020-03-31

申请号：US15861140

申请日：2018-01-03

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Chengjie Zuo ,  David Francis Berdy ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L27/01 ,  H01L23/15 ,  H01L23/522 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01G2/02 ,  H01G4/005

Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

公开(公告)号：US10290414B2

公开(公告)日：2019-05-14

申请号：US14841132

申请日：2015-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Je-Hsiung Jeffrey Lan ,  Jonghae Kim ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H01F5/00 ,  H01F27/28 ,  H01F27/245 ,  H01F41/14 ,  H01F41/04 ,  H01F17/00 ,  H01F41/32 ,  H01L23/64 ,  H05K1/16

Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.

公开(公告)号：US10249580B2

公开(公告)日：2019-04-02

申请号：US15190158

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L23/64 ,  H01F41/04 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L27/08

Abstract: In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.

公开(公告)号：US10242957B2

公开(公告)日：2019-03-26

申请号：US14633934

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  David Francis Berdy ,  Chengjie Zuo ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L23/60 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/552

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.