公开(公告)号：US10332582B2

公开(公告)日：2019-06-25

申请号：US15667618

申请日：2017-08-02

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US10090040B1

公开(公告)日：2018-10-02

申请号：US15472622

申请日：2017-03-29

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Chun ,  Yanru Li

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.

公开(公告)号：US20180260320A1

公开(公告)日：2018-09-13

申请号：US15457899

申请日：2017-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  William Kimberly

IPC: G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/32

CPC classification number: G06F12/0246 ,  G06F1/3221 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/5016 ,  G06F9/5094 ,  G06F13/1673 ,  G06F13/4068 ,  G06F2212/7201 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/22

Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.

公开(公告)号：US20180197594A1

公开(公告)日：2018-07-12

申请号：US15400507

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Jungwon Suh

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4091

CPC classification number: G11C11/408 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/4091

Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

公开(公告)号：US09983930B2

公开(公告)日：2018-05-29

申请号：US15243623

申请日：2016-08-22

Applicant: QUALCOMM INCORPORATED

Inventor： Nhon Quach ,  Yanru Li ,  Rahul Gulati

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/04 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1052 ,  G11C29/04 ,  G11C29/52

Abstract: Systems and methods are disclosed for implementing error correction control regions (ECC) in a memory device without the need to ECC protect the entire memory device. An exemplary method comprises defining one or more ECC regions in a memory device, the memory device coupled to a system on a chip (SoC). An ECC block is provided on the SoC, the ECC block in communication with the one or more ECC regions in the memory device. A determination is made with the ECC block whether to store data in a first of the one or more ECC regions. Responsive to the determination ECC bits are generating for, and interleaved with, the received data and interleaved ECC bits and data are caused to be written to the first ECC region. Otherwise, received data is sent to a non-ECC region of the memory device.

公开(公告)号：US09779798B1

公开(公告)日：2017-10-03

申请号：US15400515

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Jungwon Suh ,  Alexander Gantman

IPC: G11C7/00 ,  G11C11/4078 ,  G11C11/406

CPC classification number: G11C8/12 ,  G11C7/1063 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/4087

Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

公开(公告)号：US20170169902A1

公开(公告)日：2017-06-15

申请号：US14970273

申请日：2015-12-15

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  Yanru Li

IPC: G11C29/42 ,  G06F11/10 ,  G06F12/02 ,  G06F13/24 ,  G11C7/10 ,  G06F12/08

CPC classification number: G11C29/42 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1064 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/0875 ,  G06F13/24 ,  G11C7/1072

Abstract: Systems, methods, and computer programs are disclosed for resolving dynamic random access memory (DRAM) defects. One embodiment is a system comprising a dynamic random access memory (DRAM) system electrically coupled to a system on chip (SoC). The SoC comprises a cache and a cache controller. The cache controller is configured to store corrected data for a failed physical codeword address associated with the DRAM in the cache and provide further access to the failed physical codeword address from the cache instead of the DRAM system.

公开(公告)号：US09632562B2

公开(公告)日：2017-04-25

申请号：US14616720

申请日：2015-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： Nhon Toai Quach ,  Virat Deepak ,  Oscar Cabral Arias ,  Yanru Li ,  Haw-Jing Lo ,  Michael Drop ,  Venkata Narayana Ramesh Pinnamaraju Durga ,  Moinul Khan

IPC: G06F1/32 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/401 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

公开(公告)号：US09472261B1

公开(公告)日：2016-10-18

申请号：US14690204

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Yanru Li

IPC: G11C5/00 ,  G11C7/00 ,  G11C29/00 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/42 ,  G11C29/36

CPC classification number: G11C11/40626 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/36 ,  G11C29/42 ,  G11C29/50016 ,  G11C2207/2245 ,  G11C2211/4062

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract translation: 公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。 一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

公开(公告)号：US09431077B2

公开(公告)日：2016-08-30

申请号：US13798803

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Amit Gil ,  Erez Tsidon ,  Yanru Li ,  Azzedine Touzni

IPC: G06F9/52 ,  G06F9/54 ,  G11C7/10 ,  G06F1/32 ,  G06F9/46 ,  G06F11/07

CPC classification number: G11C7/1075 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/462 ,  G06F9/463 ,  G06F9/52 ,  G06F9/544 ,  G06F11/0757 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.

Abstract translation: 描述了使用多端口共享非易失性存储器的有效技术，其减少了诸如调制解调器控制处理器之类的专用功能特定处理器的存储器访问中的延迟。 调制解调器处理器抢占正在从多端口共享非易失性存储器闪存器件访问数据的主处理器，允许调制解调器处理器快速访问闪存设备中的数据。 抢占过程使用由寻求访问并中断处理器被抢占的处理器发起的门铃中断。 抢占后，主机处理器可以恢复或重新启动数据访问。 处理器的访问控制利用硬件信号量原子控制机制。 共享的非易失性存储器模块的功率控制包括至少一个不活动定时器，以指示何时可以安全地减少或关闭共享的非易失性存储器模块的电源电压。 共享内存的任何处理器可能会重新启动电源，从而可以快速访问数据。