公开(公告)号：US10152408B2

公开(公告)日：2018-12-11

申请号：US14566411

申请日：2014-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F12/00 ,  G06F12/02

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

公开(公告)号：US09741424B2

公开(公告)日：2017-08-22

申请号：US15271148

申请日：2016-09-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C7/00 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C8/18 ,  G11C7/22 ,  G06F1/10 ,  G11C11/409 ,  G11C11/4096 ,  G06F1/06 ,  G06F1/12 ,  G06F3/06 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

公开(公告)号：US09667406B2

公开(公告)日：2017-05-30

申请号：US14695597

申请日：2015-04-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C7/04 ,  H04L7/033

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US09652176B2

公开(公告)日：2017-05-16

申请号：US14449610

申请日：2014-08-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC: G06F3/06 ,  G11C8/06 ,  G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4097

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US09628257B2

公开(公告)日：2017-04-18

申请号：US14932192

申请日：2015-11-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C7/04 ,  H04L7/033

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US09472262B2

公开(公告)日：2016-10-18

申请号：US15070376

申请日：2016-03-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C8/00 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C8/18 ,  G11C7/22 ,  G06F1/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Abstract translation: 存储器控制器组件包括发射电路和调整电路。 发送电路使用定时信号发送时钟信号并将数据写入DRAM，由DRAM采样的写入数据。 调整电路调整写入数据和定时信号的发送定时，使得定时信号的边沿转换与DRAM处的时钟信号的边沿转换对齐。

公开(公告)号：US09311976B2

公开(公告)日：2016-04-12

申请号：US14523922

申请日：2014-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C8/18 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

Abstract translation: 具有集成电路（IC）组件，终端结构，地址/控制信号路径，时钟信号路径，多个数据信号路径和多个选通信号路径的存储模块。 选通信号路径和数据信号路径耦合到相应的IC组件，并且地址/控制信号路径和时钟信号路径共同耦合到所有IC组件。 地址/控制信号路径沿着IC组件延伸到终端结构，使得朝向终端结构传播的控制信号在对应于IC组件的相对位置的逐渐更新的时间到达各个IC组件的地址/控制输入。

公开(公告)号：US09292223B2

公开(公告)日：2016-03-22

申请号：US13901014

申请日：2013-05-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097 ,  G11C7/22

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US09170894B2

公开(公告)日：2015-10-27

申请号：US14200665

申请日：2014-03-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract translation: 提供了用于检测和校正存储器系统中的地址错误的系统和方法。 在存储器系统中，存储器件基于通过地址总线发送的地址生成错误检测码，并将错误检测码发送到存储器控制器。 存储器控制器响应于错误检测码向存储器件发送错误指示。 错误指示使存储器件移除接收的地址并防止存储器操作。

公开(公告)号：US09135186B2

公开(公告)日：2015-09-15

申请号：US14683290

申请日：2015-04-10

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F12/10 ,  G06F13/40 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。