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    Semiconductor device
    41.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09001549B2

    公开(公告)日：2015-04-07

    申请号：US13890002

    申请日：2013-05-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuya Onuki

    IPC: G11C7/00 ,  G11C5/06 ,  G11C5/10 ,  G11C14/00

    CPC classification number: G11C5/063 ,  G11C5/10 ,  G11C14/0063

    Abstract: To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored.

    Abstract translation: 为了提供在操作中具有高可靠性的半导体器件，其中易失性存储器中的数据可被保存到非易失性存储器。 例如，半导体器件包括设置有第一和第二数据存储部分的SRAM和设置有第三和第四数据存储部分的非易失性存储器。 第一数据存储部分通过晶体管电连接到第四数据存储部分，并且第二数据存储部分通过晶体管电连接到第三数据存储部分。 当SRAM工作时晶体管截止，当SRAM不工作时，晶体管导通，使得SRAM中的数据被保存到非易失性存储器中。 当SRAM恢复时，进行预充电。

    METHOD FOR DRIVING SEMICONDUCTOR DEVICE
    42.
    发明申请
    METHOD FOR DRIVING SEMICONDUCTOR DEVICE 有权
    驱动半导体器件的方法

    公开(公告)号：US20130162306A1

    公开(公告)日：2013-06-27

    申请号：US13721120

    申请日：2012-12-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki Inoue ,  Tatsuya Onuki

    IPC: H03K17/06

    CPC classification number: H03K17/063 ,  G11C11/403 ,  G11C2211/4016

    Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level

    Abstract translation: 提供了一种用于驱动半导体器件的方法，其允许减小电路的规模，降低功耗，并且提高读取数据的速度。 将H电平（数据“1”）电位或L电平（数据“0”）电位写入存储单元的节点。 源极线和位线的电位在M电平（L电平

    Semiconductor device and method for driving semiconductor device
    43.
    发明授权
    Semiconductor device and method for driving semiconductor device 有权

    公开(公告)号：US12223904B2

    公开(公告)日：2025-02-11

    申请号：US18569779

    申请日：2022-06-23

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki Okamoto ,  Tatsuya Onuki ,  Hidetomo Kobayashi ,  Munehiro Kozuma ,  Takanori Matsuzaki ,  Susumu Kawashima ,  Yutaka Okazaki

    IPC: G09G3/3233 ,  H01L27/088 ,  H01L27/12

    Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

    Memory device and semiconductor device including the memory device
    46.
    发明授权
    Memory device and semiconductor device including the memory device 有权

    公开(公告)号：US12063770B2

    公开(公告)日：2024-08-13

    申请号：US17414614

    申请日：2019-11-15

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Tatsuya Onuki

    IPC: H10B12/00 ,  H01L29/786

    CPC classification number: H10B12/30 ,  H01L29/7869

    Abstract: A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.

    Semiconductor Device, Semiconductor Wafer, and Electronic Device
    48.
    发明公开
    Semiconductor Device, Semiconductor Wafer, and Electronic Device 审中-公开

    公开(公告)号：US20240154040A1

    公开(公告)日：2024-05-09

    申请号：US18411830

    申请日：2024-01-12

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Eri SATO ,  Tatsuya Onuki ,  Yuto Yakubo ,  Hitoshi Kunitake

    IPC: H01L29/786 ,  H01L29/24

    CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678

    Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

    Memory device
    49.
    发明授权
    Memory device 有权

    公开(公告)号：US11961916B2

    公开(公告)日：2024-04-16

    申请号：US17261665

    申请日：2019-07-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Tomoaki Atsumi ,  Shunpei Yamazaki

    IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H10B12/00

    CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/78696 ,  H10B12/31

    Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

    Semiconductor device comprising transistors with silicon and metal oxide channels
    50.
    发明授权
    Semiconductor device comprising transistors with silicon and metal oxide channels 有权

    公开(公告)号：US11948626B2

    公开(公告)日：2024-04-02

    申请号：US17439876

    申请日：2020-03-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Seiya Saito ,  Yuto Yakubo ,  Tatsuya Onuki ,  Shuhei Nagatsuka

    IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4097 ,  H01L29/786 ,  H10B12/00

    CPC classification number: G11C11/4097 ,  G11C11/4091 ,  H01L29/7869 ,  H10B12/30 ,  H10B12/50

    Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.

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