公开(公告)号：US10199373B2

公开(公告)日：2019-02-05

申请号：US15648211

申请日：2017-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Zia Hossain ,  Chun-Li Liu ,  Jason McDonald ,  Ali Salih ,  Alexander Young

IPC: H01L29/417 ,  H01L27/06 ,  H01L27/02 ,  H01L23/367 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8258 ,  H01L21/74 ,  H01L29/872 ,  H01L23/48 ,  H01L29/861 ,  H01L29/20

Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

公开(公告)号：US10163764B2

公开(公告)日：2018-12-25

申请号：US15690773

申请日：2017-08-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L29/20 ,  H01L29/16 ,  H01L23/373

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US10056499B2

公开(公告)日：2018-08-21

申请号：US15254837

申请日：2016-09-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman

IPC: H01L29/15 ,  H01L29/808 ,  H01L29/20 ,  H01L29/423 ,  H01L29/43 ,  H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/8083 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1602 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/2203 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/66909 ,  H01L29/66924

Abstract: An electronic device comprising a bidirectional JFET can include a drain/source region; a lightly doped semiconductor layer overlying the drain/source region; a source/drain region overlying the lightly doped semiconductor layer; a trench extending through the source/drain region and into the lightly doped semiconductor layer; a gate electrode of the bidirectional JFET within the trench; and a field electrode within the trench. A process of forming an electronic device can include providing a workpiece including a first doped region and a lightly doped semiconductor layer overlying the first doped region; defining a trench extending into the lightly doped semiconductor layer; forming a gate electrode within the trench, wherein the gate electrode extends to a sidewall of the trench; and forming a field electrode within the trench, wherein a bidirectional JFET includes the first doped region, the lightly doped semiconductor layer, a second doped region, and the gate electrode.

公开(公告)号：US20180166557A1

公开(公告)日：2018-06-14

申请号：US15882478

申请日：2018-01-29

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/78 ,  H01L29/778 ,  H01L29/417

CPC classification number: H01L29/66462 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41758 ,  H01L29/66537 ,  H01L29/66704 ,  H01L29/7787 ,  H01L29/7823 ,  H01L29/7825

Abstract: In accordance with an embodiment, a cascode connected semiconductor component and a method for manufacturing the cascode connected semiconductor component are provided. The cascode connected semiconductor component has a pair of silicon based transistors, each having a body region, a gate region over the body region, a source region and a drain. The source regions of a first and second silicon based transistor are electrically connected together and the drain regions of the first and second silicon based transistors are electrically connected together. The gate region of the second silicon based transistor is connected to the drain regions of the first and second silicon based transistors. The body region of the second silicon based transistor has a dopant concentration that is greater than the dopant concentration of the first silicon based transistor. A gallium nitride based transistor has a source region coupled to the first and second silicon based transistor.

公开(公告)号：US20180005927A1

公开(公告)日：2018-01-04

申请号：US15690773

申请日：2017-08-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/373 ,  H01L29/20 ,  H01L29/16

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/32145 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US09780196B2

公开(公告)日：2017-10-03

申请号：US15261308

申请日：2016-09-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66666 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

Abstract: In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

公开(公告)号：US09780019B2

公开(公告)日：2017-10-03

申请号：US15207626

申请日：2016-07-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L29/20 ,  H01L29/16 ,  H01L23/373

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US09741711B2

公开(公告)日：2017-08-22

申请号：US14853729

申请日：2015-09-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Zia Hossain ,  Chun-Li Liu ,  Woochul Jeon ,  Jason McDonald

IPC: H01L29/66 ,  H01L21/70 ,  H01L27/06 ,  H01L27/02 ,  H01L23/367 ,  H01L29/417 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8258 ,  H01L21/74 ,  H01L29/872 ,  H01L23/48 ,  H01L29/861 ,  H01L29/20

CPC classification number: H01L27/0629 ,  H01L21/743 ,  H01L21/8258 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0688 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

公开(公告)号：US20170221752A1

公开(公告)日：2017-08-03

申请号：US15487517

申请日：2017-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/762 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/743 ,  H01L21/746 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/76898 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/66318 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7786

Abstract: In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US20170025335A1

公开(公告)日：2017-01-26

申请号：US15202765

申请日：2016-07-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/45

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/73 ,  H01L25/072 ,  H01L29/2003 ,  H01L33/62 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.

Abstract translation: 根据实施例，提供了半导体部件，其包括具有器件接收区域的引线框架，一个或多个引线框架引线以及结合到器件接收区域的第一部分的至少一个绝缘金属衬底。 第一半导体器件安装到第一绝缘金属衬底，第一半导体器件由III-N半导体材料构成。 第一电互连耦合在第一半导体器件的第一载流端子和管芯接收区域的第二部分之间。 根据另一实施例，方法包括提供包括III-N半导体衬底材料的第一半导体芯片和包括硅基半导体衬底的第二半导体芯片。 第一半导体芯片安装在第一基板上，第二半导体芯片安装在第二基板上。 第一半导体芯片电耦合到第二半导体芯片。