公开(公告)号：US09230970B2

公开(公告)日：2016-01-05

申请号：US14595692

申请日：2015-01-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Shuhei Nagatsuka

IPC: H01L27/088 ,  H01L27/11 ,  H01L27/06 ,  H01L27/12 ,  H01L49/02 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/1108 ,  G11C16/0408 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

Abstract: A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.

公开(公告)号：US20150311323A1

公开(公告)日：2015-10-29

申请号：US14740688

申请日：2015-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: H01L29/66 ,  H01L21/425 ,  H01L27/115 ,  H01L21/441 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US09105511B2

公开(公告)日：2015-08-11

申请号：US14336107

申请日：2014-07-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/115 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L29/78

CPC classification number: H01L27/1052 ,  G11C11/405 ,  G11C16/0433 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7833 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract translation: 目的是提供具有新颖结构的半导体器件。 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管设置在包括半导体材料的衬底中。 第二晶体管包括氧化物半导体层。

公开(公告)号：US20150187775A1

公开(公告)日：2015-07-02

申请号：US14582319

申请日：2014-12-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Kiyoshi Kato

IPC: H01L27/108 ,  G11C7/12 ,  G11C5/14 ,  G11C11/419

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

Abstract translation: 可以写入和读取多级数据的新型半导体器件。 半导体器件包括第一至第五晶体管，电容器，位线和电源线。 以通过第一晶体管将第一数据提供给第五晶体管的栅极的方式执行写入操作; 第一个晶体管关闭; 第二数据通过第二晶体管提供给电容器的第二电极，以将第一数据转换为第三数据; 并且使电容器的第二电极电浮动。 电容器的第二个电极通过第三个晶体管初始化为GND。 通过对第四晶体管和第五晶体管的位线进行充电或放电来进行读操作。 第一至第三晶体管优选为氧化物半导体晶体管。

公开(公告)号：US09059689B2

公开(公告)日：2015-06-16

申请号：US14160774

申请日：2014-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K5/04 ,  H03K5/06 ,  H03K5/05 ,  H03K5/00

CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K2005/00104 ,  H03K2005/00241

Abstract: To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.

Abstract translation: 提供能够调整时钟信号或高质量半导体器件的定时的半导体器件。 半导体器件包括第一晶体管和包括第二晶体管的电路。 第一晶体管的沟道形成在氧化物半导体层中。 第一信号被输入到第一晶体管的源极和漏极之一。 第一晶体管的源极和漏极中的另一个电连接到第二晶体管的栅极。 第一时钟信号被输入到电路。 电路输出第二个时钟信号。 第二时钟信号的定时与第一时钟信号的定时不同。

公开(公告)号：US20140340127A1

公开(公告)日：2014-11-20

申请号：US14277248

申请日：2014-05-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidetomo Kobayashi ,  Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K3/012

CPC classification number: G09G3/00 ,  G09G2330/022 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/7833 ,  H03K19/0016

Abstract: A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film.

Abstract translation: 具有短占空时间的半导体器件。 所述半导体器件包括供给电源电位的第一布线，第二布线，用于控制所述第一布线和所述第二布线之间的电连接的开关，电连接到所述第二布线的负载，源极和漏极电连接的晶体管 连接到第二布线，以及功率管理单元，具有控制开关的导通状态和控制晶体管的栅极电位的功能。 晶体管的沟道形成区域包括在氧化物半导体膜中。

公开(公告)号：US20140269063A1

公开(公告)日：2014-09-18

申请号：US14201068

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/08

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 放电位线的电荷，通过用于写入数据的晶体管对位线的电位进行充电，并且通过充电而改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US08835271B2

公开(公告)日：2014-09-16

申请号：US13857659

申请日：2013-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

IPC: H01L33/52 ,  H01L27/12 ,  G02F1/1362 ,  H01L27/32 ,  H01L27/13 ,  H01L51/52

CPC classification number: H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

Abstract translation: 本发明的目的是提供一种具有层间绝缘膜的半导体显示装置，其可以在控制成膜时间的同时获得表面的平面性，并且可以控制用于除去水分的加热处理的处理时间，并且可以防止水分 在层间绝缘膜中不被放电到与层间绝缘膜相邻的膜或电极。 形成与有机树脂相比不容易透过水分的含氮的无机绝缘膜，以覆盖TFT。 接着，在有机绝缘膜上涂布含有感光性丙烯酸树脂的有机树脂膜，将有机树脂膜部分地曝光以打开。 然后，形成与有机树脂相比不容易透过水分的含有氮的无机绝缘膜，以覆盖打开的有机树脂膜。 然后，在有机树脂膜的开口部分中，通过蚀刻部分地打开栅极绝缘膜和含氮的两层无机绝缘膜，以暴露TFT的有源层。

公开(公告)号：US20140231882A1

公开(公告)日：2014-08-21

申请号：US14266930

申请日：2014-05-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

IPC: G06K19/07 ,  H01L27/13 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

Abstract translation: 本发明提供一种处理器，其通过在对热敏感的基板（例如塑料基板或塑料膜基板）上形成使用多晶半导体的高功能集成电路。 此外，本发明提供一种无线发送和接收电力或信号的无线处理器，无线存储器及其信息处理系统。 根据本发明，一种信息处理系统包括一个元件形成区域，该元件形成区域包括晶体管，该晶体管至少具有由半导体膜形成的沟道形成区域，所述半导体膜片分隔成10至200nm的厚度的岛状物以及天线。 晶体管固定在柔性基板上。 其中形成包括元件形成区域的高功能集成电路并且半导体器件通过天线发送和接收数据的无线处理器。

公开(公告)号：US08811067B2

公开(公告)日：2014-08-19

申请号：US14183644

申请日：2014-02-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: G11C11/24

CPC classification number: G11C7/12 ,  G11C11/24 ,  G11C11/405 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

Abstract translation: 目的在于提供一种具有新颖结构的半导体器件。 第一个接线 第二布线 第三布线，第四布线; 第一晶体管，包括第一栅极电极，第一源极电极和第一漏极电极; 包括第二晶体管，包括第二栅电极，第二源电极和第二漏电极。 第一晶体管设置在包括半导体材料的衬底上，并且第二晶体管包括氧化物半导体层。