公开(公告)号：US20100144128A1

公开(公告)日：2010-06-10

申请号：US12703478

申请日：2010-02-10

Applicant: Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

Inventor： Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

IPC: H01L21/36 ,  H01L21/00

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/53 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1675

Abstract: A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion.

Abstract translation: 相变存储单元包括由相变元件电耦合的第一和第二电极。 相变元件的至少一部分包括较高的复位转变温度部分和较低的复位转变温度部分。 下复位转变温度部分包括可以通过电流通过从相对于较高复位转变温度部分的较低温度的大致结晶到大致非晶状态的相变区域。 相变元件可以包括围绕内部，下部复位转变温度部分的外部，大体上管状的较高复位转变温度部分。

公开(公告)号：US20100117049A1

公开(公告)日：2010-05-13

申请号：US12267492

申请日：2008-11-07

Applicant: HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

Inventor： HSIANG-LAN LUNG ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC: H01L47/00 ,  H01L21/36

CPC classification number: H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

Abstract translation: 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

公开(公告)号：US07579613B2

公开(公告)日：2009-08-25

申请号：US11959708

申请日：2007-12-19

Applicant: Hsiang Lan Lung ,  Shih-Hung Chen

Inventor： Hsiang Lan Lung ,  Shih-Hung Chen

IPC: H01L29/02

CPC classification number: H01L45/1226 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

Abstract: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. In the array, a plurality of electrode members and insulating members therebetween comprise an electrode layer on an integrated circuit. The bridges of memory material have sub-lithographic dimensions.

Abstract translation: 一种存储器件，包括具有顶侧的第一电极，具有顶侧的第二电极和位于第一电极和第二电极之间的绝缘构件。 绝缘构件在第一电极的顶侧附近和第二电极的顶侧之间具有在第一和第二电极之间的厚度。 记忆材料桥跨越绝缘构件，并且在绝缘构件之间限定了第一和第二电极之间的电极间路径。 提供这样的存储单元阵列。 在阵列中，多个电极构件和绝缘构件包括集成电路上的电极层。 记忆材料的桥梁具有亚光刻尺寸。

公开(公告)号：US20090194758A1

公开(公告)日：2009-08-06

申请号：US12026342

申请日：2008-02-05

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/79 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater material is on the first phase change material. A second phase change layer comprising a second phase change material is on the resistive heater, and a top electrode is on the second phase change layer. The heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials.

Abstract translation: 存储器件与制造方法一起被描述。 如本文所述的存储器件包括底部电极和在底部电极上包括第一相变材料的第一相变层。 包括加热器材料的电阻加热器位于第一相变材料上。 包括第二相变材料的第二相变层位于电阻加热器上，顶电极位于第二相变层上。 加热器材料的电阻率大于第一和第二相变材料的最高电阻状态。

公开(公告)号：US07442603B2

公开(公告)日：2008-10-28

申请号：US11465094

申请日：2006-08-16

Applicant: Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

Inventor： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC: H01L27/13

CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

Abstract translation: 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US07238994B2

公开(公告)日：2007-07-03

申请号：US11155202

申请日：2005-06-17

Applicant: Shih-Hung Chen ,  Hsiang Lan Lung

Inventor： Shih-Hung Chen ,  Hsiang Lan Lung

IPC: H01L29/76 ,  H01L29/00

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

Abstract: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

Abstract translation: 一种存储器件，包括存取电路，存取电路上的电极层，电极层上的相变存储器阵列，以及相变存储器桥阵列上的多个位线。 电极层包括电极对。 电极对包括具有顶侧的第一电极，具有顶侧的第二电极和在第一电极和第二电极之间的绝缘构件。 记忆材料桥跨越绝缘构件，并且在绝缘构件之间限定了第一和第二电极之间的电极间路径。

公开(公告)号：US20060284157A1

公开(公告)日：2006-12-21

申请号：US11155202

申请日：2005-06-17

Applicant: Shih-Hung Chen ,  Hsiang Lung

Inventor： Shih-Hung Chen ,  Hsiang Lung

IPC: H01L29/02

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

Abstract: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

公开(公告)号：US09240405B2

公开(公告)日：2016-01-19

申请号：US13089652

申请日：2011-04-19

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

IPC: H01L27/118 ,  H01L27/06 ,  H01L27/02 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/0688 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

Abstract translation: 描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。 用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。 存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。 存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。 这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。 然后可以将单独的电路堆叠并结合在一起。

公开(公告)号：US09224611B2

公开(公告)日：2015-12-29

申请号：US13570411

申请日：2012-08-09

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H03K3/00 ,  H01L21/28 ,  H01L23/48 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/0001

Abstract: A semiconductor structure and a manufacturing method and an operating method of the same are provided. The semiconductor structure includes a substrate, a main body structure, a first dielectric layer, a first conductive strip, a second conductive strip, a second dielectric layer, and a conductive structure. The main body structure is formed on the substrate, and the first dielectric layer is formed on the substrate and surrounding two sidewalls and a top portion of the main body structure. The first conductive strip and the second conductive strip are formed on two sidewalls of the first dielectric layer, respectively. The second dielectric layer is formed on the first dielectric layer, the first conductive strip, and the second conductive strip. The conductive structure is formed on the second dielectric layer.

Abstract translation: 提供了一种半导体结构及其制造方法及其操作方法。 半导体结构包括基板，主体结构，第一介电层，第一导电条，第二导电条，第二介电层和导电结构。 主体结构形成在基板上，第一电介质层形成在基板上并围绕主体结构的两个侧壁和顶部。 第一导电条和第二导电条分别形成在第一介电层的两个侧壁上。 第二电介质层形成在第一电介质层，第一导电条和第二导电条上。 导电结构形成在第二电介质层上。

公开(公告)号：US08860202B2

公开(公告)日：2014-10-14

申请号：US13597669

申请日：2012-08-29

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L23/02

CPC classification number: H01L23/36 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed above the first chip. The vertical conductive line is electrically connected to the first chip and the second chip. The vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip.

Abstract translation: 提供了芯片堆叠结构及其制造方法。 芯片堆叠结构包括第一芯片，第二芯片和垂直导线。 第二芯片设置在第一芯片上方。 垂直导线与第一芯片和第二芯片电连接。 垂直导线设置在第一芯片和第二芯片的投影区域的外侧。