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    VECTOR MAXIMUM AND MINIMUM WITH INDEXING
    41.
    发明申请
    VECTOR MAXIMUM AND MINIMUM WITH INDEXING 有权

    公开(公告)号：US20210216313A1

    公开(公告)日：2021-07-15

    申请号：US17215013

    申请日：2021-03-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

    IPC: G06F9/30

    Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
    44.
    发明申请
    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING 审中-公开

    公开(公告)号：US20180365122A1

    公开(公告)日：2018-12-20

    申请号：US16112996

    申请日：2018-08-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

    IPC: G06F11/30 ,  G06F13/16 ,  G06F11/00 ,  G06F12/0875 ,  G06F11/27 ,  G06F12/0862 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

    Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

    Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors
    46.
    发明授权
    Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors 有权
    通过分布式延迟检测和软错误校正保护存储器，数据通路和流水线寄存器以及其他存储元件

    公开(公告)号：US09557936B2

    公开(公告)日：2017-01-31

    申请号：US14587234

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  David M. Thompson ,  Jonathan (Son) Hung Tran ,  Ramakrishnan Venkatasubramanian

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

    Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

    Abstract translation: 本发明是数据处理装置和方法。 通过产生对应于该数据的纠错码，使用纠错码来防止数据损坏。 在本发明中，将数据和相应的纠错码转发到另一组寄存器，而不用再生纠错码或使用纠错码进行错误检测或校正。 只有以后才采取纠错检测和纠正措施。 在数据处理装置中不同的数据/纠错码寄存器可能处于不同的流水线相位。 本发明通过携带数据的整个数据路径转发具有数据的纠错码。 本发明为整个数据路径提供错误保护，而不需要大量硬件或额外的时间。

    Three-term predictive adder and/or subtracter
    47.
    发明授权
    Three-term predictive adder and/or subtracter 有权
    三项预测加法器和/或减法器

    公开(公告)号：US09448767B2

    公开(公告)日：2016-09-20

    申请号：US14192102

    申请日：2014-02-27

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

    IPC: G06F7/50 ,  G06F7/57 ,  G06F7/505 ,  G06F7/506

    CPC classification number: G06F7/57 ,  G06F7/5055 ,  G06F7/506

    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

    Abstract translation: 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

    Three-Term Predictive Adder and/or Subtracter
    48.
    发明申请
    Three-Term Predictive Adder and/or Subtracter 审中-公开
    三阶预测加法器和/或减法器

    公开(公告)号：US20140181165A1

    公开(公告)日：2014-06-26

    申请号：US14192102

    申请日：2014-02-27

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

    IPC: G06F7/57

    CPC classification number: G06F7/57 ,  G06F7/5055 ,  G06F7/506

    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

    Abstract translation: 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示波纹部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

    Multi Domain Bridge with Auto Snoop Response
    49.
    发明申请
    Multi Domain Bridge with Auto Snoop Response 有权
    具有自动侦测响应的多域网桥

    公开(公告)号：US20140115269A1

    公开(公告)日：2014-04-24

    申请号：US14031390

    申请日：2013-09-19

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel B. Wu ,  Timothy D. Anderson

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain-master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.

    Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 掉电机制与主站和互连之间实现的异步桥隔离，主站与异步桥之间的基本请求/确认握手。

    Multiple instruction set architectures on a processing device
    50.
    发明授权
    Multiple instruction set architectures on a processing device 有权

    公开(公告)号：US12260219B2

    公开(公告)日：2025-03-25

    申请号：US18355939

    申请日：2023-07-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Duc Bui ,  Timothy D. Anderson ,  Paul Gauvreau

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

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