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    Biosensor with a sensing surface on an interlayer dielectric
    41.
    发明授权
    Biosensor with a sensing surface on an interlayer dielectric 有权
    生物传感器在层间电介质上具有感测表面

    公开(公告)号：US09488615B2

    公开(公告)日：2016-11-08

    申请号：US14573162

    申请日：2014-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Wen Cheng ,  Fei-Lung Lai ,  Chia-Hua Chu ,  Yi-Hsien Chang ,  Hsin-Chieh Huang

    IPC: G01N27/414 ,  H01L23/498 ,  H01L21/48

    CPC classification number: G01N27/4148 ,  G01N27/4145 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor having horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a semiconductor substrate. A back-end-of the line (BEOL) metallization stack with a plurality of metal interconnect layers electrically coupled to the sensing device is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. A sensing well is located within a top surface of the ILD layer. The sensing well has a horizontal sensing surface extending along a top surface of a first one of the plurality of metal interconnect layers and a vertical sensing surface extending along a sidewall of a second one of the plurality of metal interconnect layers overlying the first one of the plurality of metal interconnect layers. The use of both horizontal and vertical sensing surfaces enables more accurate sensing.

    Abstract translation: 本公开涉及具有集成的生物传感器的集成芯片，其具有水平和垂直的感测表面。 在一些实施例中，集成芯片具有设置在半导体衬底内的感测装置。 具有电耦合到感测装置的多个金属互连层的线路后端（BEOL）金属化堆叠被布置在覆盖半​​导体衬底的层间电介质（ILD）层内。 感测井位于ILD层的顶表面内。 感测井具有沿着多个金属互连层中的第一个的顶表面延伸的水平感测表面和垂直感测表面，该垂直感测表面沿着多个金属互连层中的第一个上的第一个金属互连层的第二个 多个金属互连层。 使用水平和垂直传感表面可以实现更准确的感测。

    Method for the integration of a microelectromechanical systems (MEMS) microphone device with a complementary metal-oxide-semiconductor (CMOS) device
    42.
    发明授权
    Method for the integration of a microelectromechanical systems (MEMS) microphone device with a complementary metal-oxide-semiconductor (CMOS) device 有权
    用于将微机电系统（MEMS）麦克风装置与互补金属氧化物半导体（CMOS）器件集成的方法

    公开(公告)号：US09386380B2

    公开(公告)日：2016-07-05

    申请号：US14524074

    申请日：2014-10-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

    IPC: H04R19/00 ,  H04R19/04 ,  H04R31/00

    CPC classification number: H04R19/005 ,  H04R19/04 ,  H04R31/006

    Abstract: A microelectromechanical systems (MEMS) package includes a MEMS device and an integrated circuit (IC) device connected by a through silicon via (TSV). A conductive MEMS structure is arranged in a dielectric layer and includes a membrane region extending across a first volume arranged in the dielectric layer. A first substrate is bonded to a second substrate through the dielectric layer, where the MEMS device includes the second substrate. The TSV extends through the second substrate to electrically couple the MEMS device to the IC device. A third substrate is bonded to the second substrate to define a second volume between the second substrate and the third substrate, where the IC device includes the first or third substrate. A method for manufacturing the MEMS package is also provided.

    Abstract translation: 微机电系统（MEMS）封装包括MEMS器件和通过硅通孔（TSV）连接的集成电路（IC）器件。 导电MEMS结构布置在电介质层中，并且包括跨过设置在电介质层中的第一体积延伸的膜区域。 第一衬底通过介电层结合到第二衬底，其中MEMS器件包括第二衬底。 TSV延伸穿过第二衬底以将MEMS器件电耦合到IC器件。 第三基板被结合到第二基板以在第二基板和第三基板之间限定第二体积，其中IC器件包括第一或第三基板。 还提供了一种制造MEMS封装的方法。

    MEMS AND CMOS INTEGRATION WITH LOW-TEMPERATURE BONDING
    43.
    发明申请
    MEMS AND CMOS INTEGRATION WITH LOW-TEMPERATURE BONDING 有权
    MEMS和CMOS集成与低温接合

    公开(公告)号：US20160137492A1

    公开(公告)日：2016-05-19

    申请号：US14639492

    申请日：2015-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Wen Cheng ,  Chia-Hua Chu ,  Jung-Huei Peng

    IPC: B81C1/00 ,  B81B7/00 ,  B81B3/00

    CPC classification number: B81C1/00238 ,  B81B3/001 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2201/0132 ,  B81C2203/035 ,  B81C2203/037 ,  B81C2203/0792 ,  H01L2224/16

    Abstract: The present disclosure relates to method of forming a MEMS device that mitigates the above mentioned difficulties. In some embodiments, the present disclosure relates to a method of forming a MEMS device, which forms one or more cavities within a first side of a carrier substrate. The first side of the carrier substrate is then bonded to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate, and the MEMS substrate is subsequently patterned to define a soft mechanical structure over the one or more cavities. The dielectric layer is then selectively removed, using a dry etching process, to release the one or more soft mechanical structures. A CMOS substrate is bonded to a second side of the MEMS substrate, by way of a bonding structure disposed between the CMOS substrate and the MEMS substrate, using a low-temperature bonding process.

    Abstract translation: 本公开涉及形成减轻上述困难的MEMS器件的方法。 在一些实施例中，本公开涉及一种形成MEMS器件的方法，所述MEMS器件在载体衬底的第一侧内形成一个或多个空腔。 然后将载体衬底的第一侧接合到布置在微机电系统（MEMS）衬底上的电介质层，随后将MEMS衬底图案化以限定一个或多个空腔上的软机械结构。 然后使用干蚀刻工艺选择性地去除电介质层以释放一个或多个软机械结构。 通过使用低温接合工艺，通过设置在CMOS衬底和MEMS衬底之间的接合结构将CMOS衬底结合到MEMS衬底的第二侧。

    Wafer level sealing methods with different vacuum levels for MEMS sensors
    44.
    发明授权
    Wafer level sealing methods with different vacuum levels for MEMS sensors 有权
    MEMS传感器的不同真空度的晶圆级密封方法

    公开(公告)号：US09035451B2

    公开(公告)日：2015-05-19

    申请号：US14041298

    申请日：2013-09-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Kuei-Sung Chang ,  Chun-Wen Cheng

    IPC: B81B7/00 ,  B81B3/00 ,  H01L29/84 ,  H01L21/02 ,  B81C1/00

    CPC classification number: B81C1/00293 ,  B81B3/0018 ,  B81B3/0059 ,  B81B3/0067 ,  B81B7/0032 ,  B81B7/0041 ,  B81B7/02 ,  B81C1/00158 ,  B81C2203/0145 ,  H01L29/84

    Abstract: The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of cavities with different pressures on a wafer package system, and an associated apparatus. In some embodiments, the method is performed by providing a work-piece having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the work-piece in a first ambient environment having a first pressure. The bonding forms a plurality of cavities abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of cavities leading to a gas flow path that could be held at a pressure level different from the first pressure. The one or more openings in the one or more of the plurality of cavities are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of cavities to be held at the different pressure.

    Abstract translation: 本公开涉及一种在晶片封装系统上形成具有多个具有不同压力的空腔的多个MEM器件的方法，以及相关联的装置。 在一些实施例中，该方法通过提供具有多个微机电系统（MEM）装置的工件来执行。 帽盖晶片在具有第一压力的第一周围环境中结合到工件上。 接合形成与多个保持在第一压力下的多个MEM装置邻接的多个空腔。 一个或多个开口形成在多个空腔中的一个或多个空腔中，导致可以保持在不同于第一压力的压力水平的气体流动路径。 然后将多个空腔中的一个或多个中的一个或多个开口密封在具有不同压力的不同周围环境中，从而使多个空腔中的一个或多个保持在不同的压力。

    Semiconductor structure for MEMS device
    46.
    发明授权
    Semiconductor structure for MEMS device 有权

    公开(公告)号：US11312623B2

    公开(公告)日：2022-04-26

    申请号：US16944399

    申请日：2020-07-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Jung-Huei Peng

    IPC: H01L21/00 ,  B81C1/00

    Abstract: The present disclosure relates to a method of forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a dielectric structure over a substrate. A dielectric layer arranged along a top of the dielectric structure is patterned to define a via hole exposing an uppermost one of the plurality of interconnect layers. An extension via is formed within the via hole and one or more conductive materials are formed over the dielectric layer and the extension via. The one or more conductive materials are patterned to define a sensing electrode over and electrically coupled to the extension via. A microelectromechanical systems (MEMS) substrate is bonded to the substrate. The MEMs substrate is vertically separated from the sensing electrode.

    CMOS-MEMS integration with through-chip via process
    47.
    发明授权
    CMOS-MEMS integration with through-chip via process 有权

    公开(公告)号：US11235969B2

    公开(公告)日：2022-02-01

    申请号：US16420514

    申请日：2019-05-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Wen Cheng ,  Chia-Hua Chu ,  Wen Cheng Kuo ,  Wei-Jhih Mao

    IPC: B81B7/00 ,  B81C1/00 ,  B81C3/00

    Abstract: The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.

    Particle filter for MEMS device
    50.
    发明授权
    Particle filter for MEMS device 有权

    公开(公告)号：US10941034B1

    公开(公告)日：2021-03-09

    申请号：US16542479

    申请日：2019-08-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hua Chu ,  Chun-Wen Cheng ,  Wen Cheng Kuo

    IPC: B81C1/00 ,  B81B7/00

    Abstract: Various embodiments of the present disclosure are directed towards a microphone including a particle filter disposed between a microelectromechanical systems (MEMS) substrate and a carrier substrate. A MEMS device structure overlies the MEMS substrate. The MEMS device structure includes a diaphragm having opposing sidewalls that define a diaphragm opening. The carrier substrate underlies the MEMS substrate. The carrier substrate has opposing sidewalls that define a carrier substrate opening underlying the diaphragm opening. A filter stack is sandwiched between the carrier substrate and the MEMS substrate. The filter stack includes an upper dielectric layer, a lower dielectric layer, and a particle filter layer disposed between the upper and lower dielectric layers. The particle filter layer includes the particle filter spaced laterally between the opposing sidewalls of the carrier substrate.

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