公开(公告)号：US08952329B1

公开(公告)日：2015-02-10

申请号：US14045138

申请日：2013-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chang Shih ,  Yi-Jie Chen ,  Chia-Cheng Chang ,  Feng-Yuan Chiu ,  Ying-Chou Cheng ,  Chiu Hsiu Chen ,  Bing-Syun Yeh ,  Ru-Gun Liu

IPC: G01N23/00 ,  G21K7/00 ,  G01B15/04

CPC classification number: H01L22/12 ,  G01B2210/56 ,  G03F7/70433 ,  G03F7/705

Abstract: A method for characterizing a three-dimensional surface profile of a semiconductor workpiece is provided. In this method, the three-dimensional surface profile is imaged from a normal angle to measure widths of various surfaces in a first image. The three-dimensional surface is also imaged from a first oblique angle to re-measure the widths of the various surfaces in a second image. Based on differences in widths of corresponding surfaces for first and second images, a feature height and sidewall angle are determined for the three-dimensional profile.

Abstract translation: 提供了一种用于表征半导体工件的三维表面轮廓的方法。 在该方法中，从正常角度对三维表面轮廓进行成像，以测量第一图像中的各种表面的宽度。 三维表面也从第一倾斜角度成像，以重新测量第二图像中各种表面的宽度。 基于第一和第二图像的相应表面的宽度差异，确定三维轮廓的特征高度和侧壁角度。

公开(公告)号：US20140115546A1

公开(公告)日：2014-04-24

申请号：US13657992

申请日：2012-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

Abstract translation: 本公开涉及一种用于创建用于电子束光刻的物理布局的方法和装置，包括定义用于物理设计的布局网格，所述布局网格还包括垂直网格线，其与由物理设计分割所产生的缝合线重合 多个子场。 物理设计根据设计形状和布局网格之间相互作用的设计限制进行组装。 在一些实施例中，通过布局限制来实现设计限制。 在一些实施例中，通过移动标准单元以在后布局步骤中最小化与布局格栅的设计形状交互来实现设计限制。 在一些实施例中，通过交换多个标准单元之间的位置来实现设计限制，用于交换置换，其最小化后布局步骤中的交互次数。 在一些实施例中，路由网格被改进以排除设计构造的子集与布局网格之间的交互。 然后沿着布线网格相对于缝合线优化剩余的设计形状布局。

公开(公告)号：US20240371868A1

公开(公告)日：2024-11-07

申请号：US18774323

申请日：2024-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H10B12/00

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US12113132B2

公开(公告)日：2024-10-08

申请号：US18053021

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/76871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/41791

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US11862623B2

公开(公告)日：2024-01-02

申请号：US18167651

申请日：2023-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen Young ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Shun-Li Chen ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Chun-Kuang Chen ,  Ru-Gun Liu

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/528 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US11810811B2

公开(公告)日：2023-11-07

申请号：US17869142

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC: H01L29/66 ,  H01L21/74 ,  H01L23/535 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/762 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L29/66795 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/785 ,  H10B10/12

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US11782352B2

公开(公告)日：2023-10-10

申请号：US17815155

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Jie Lee ,  Shih-Chun Huang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Yung-Sung Yen ,  Ru-Gun Liu

IPC: G03F9/00 ,  G03F7/20

CPC classification number: G03F9/7026 ,  G03F7/2004 ,  G03F7/2041

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

公开(公告)号：US11735469B2

公开(公告)日：2023-08-22

申请号：US17661600

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/768 ,  H01L21/02 ,  H01L21/263 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/2633 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76877

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US11569090B2

公开(公告)日：2023-01-31

申请号：US17384921

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/266 ,  C23C16/458 ,  C23C16/50 ,  C23C16/04

Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

公开(公告)号：US11415890B2

公开(公告)日：2022-08-16

申请号：US17195469

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting Huang ,  Shih-Hsiang Lo ,  Ru-Gun Liu

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78

Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.