公开(公告)号：US08421239B2

公开(公告)日：2013-04-16

申请号：US12724903

申请日：2010-03-16

申请人： Griselda Bonilla ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L29/40

CPC分类号： H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.

摘要翻译： 用于形成齿形导体的方法和具有齿形导体的器件包括在介电层上形成硬掩模层，并对硬掩模层进行构图。 使用硬掩模层在电介质层中蚀刻沟槽，使得沟槽具有沿着沟槽的长度交替的较浅部分和较深部分。 导体沉积在沟槽中，使得形成具有沿着导电线的长度周期性地设置的不同深度的锯齿形导电线。

公开(公告)号：US20130012017A1

公开(公告)日：2013-01-10

申请号：US13614563

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US08241992B2

公开(公告)日：2012-08-14

申请号：US12776885

申请日：2010-05-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US20120111825A1

公开(公告)日：2012-05-10

申请号：US13351370

申请日：2012-01-17

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： B05D5/12 ,  B05D3/10

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US20120032311A1

公开(公告)日：2012-02-09

申请号：US12853278

申请日：2010-08-09

申请人： Stephen M. Gates ,  Alfred Grill ,  Son V. Nguyen ,  Satyanarayana V. Nitta

发明人： Stephen M. Gates ,  Alfred Grill ,  Son V. Nguyen ,  Satyanarayana V. Nitta

IPC分类号： H01L29/06 ,  H01L23/538 ,  H01L21/314

CPC分类号： H01L29/06 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/538 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.

摘要翻译： 描述了一种原位方法，其包括等离子体增强化学气相沉积，其包括流动含有Si，Si + C，B，Si + B，Si + B + C和B + C的前体中的至少一种和含N前体 并且第二次除去N前体，并开始将氧化剂气体和致孔剂气体流入室中。 描述了一种介电层，其包括在整个网络中具有无机随机三维共价键的网络，其包含至少一种SiCN，SiCNH，SiN，SiNH，BN，BNH，CBN，CBNH，BSiN，BSiNH，SiCBN和SiCBNH作为第一组分 和作为与其相邻的第二组分的低k电介质。

公开(公告)号：US08003520B2

公开(公告)日：2011-08-23

申请号：US12972808

申请日：2010-12-20

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

公开(公告)号：US07977032B2

公开(公告)日：2011-07-12

申请号：US10906268

申请日：2005-02-11

申请人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

发明人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

IPC分类号： G03F7/20

CPC分类号： G03F7/2022

摘要： A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

摘要翻译： 提供了一种在邻接区域中对材料性质进行不同的改变的同时选择性地改变一个区域中的衬底的材料特性的方法。 该方法包括在第一曝光期间选择性地掩蔽衬底的第一部分，并且在第二次曝光期间选择性地掩蔽衬底的第二部分。 另外，可以形成具有多于一个厚度的掩模，其中每个厚度将选择性地减少来自衬底的覆盖曝光的能量的量，从而允许衬底在单次覆盖曝光中接收不同水平的能量。

公开(公告)号：US07687913B2

公开(公告)日：2010-03-30

申请号：US11676447

申请日：2007-02-19

申请人： Nirupama Chakrapani ,  Matthew E. Colburn ,  Christos D. Dimitrakopoulos ,  Dirk Pfeiffer ,  Sampath Purushothaman ,  Satyanarayana V. Nitta

发明人： Nirupama Chakrapani ,  Matthew E. Colburn ,  Christos D. Dimitrakopoulos ,  Dirk Pfeiffer ,  Sampath Purushothaman ,  Satyanarayana V. Nitta

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76826 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31058 ,  H01L21/76807 ,  H01L21/76814 ,  H01L2924/0002 ,  H01L2924/00

摘要： Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR′Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R′ are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

摘要翻译： 通常用于减少集成电路中的RC延迟的是多孔有机硅酸盐的介电膜，其具有二氧化硅像主链与烷基或芳基（以增加材料的疏水性并产生自由体积）直接附着在网络中的Si原子。 Si-R键在暴露于等离子体或通常用于加工的化学处理中很少存活; 这在具有开孔细孔结构的材料中尤其如此。 当Si-R键断裂时，材料由于形成亲水硅烷醇而损失疏水性，并且低介电常数受损。 使用新型甲硅烷基化剂回收材料的疏水性的方法，其可以具有通式（R2N）XSiR'Y，其中X和Y分别为1至3和3至1的整数，并且其中R和 R'选自氢，烷基，芳基，烯丙基和乙烯基部分。 由于甲硅烷基化处理，多孔有机硅酸盐的机械强度也得到改善。

公开(公告)号：US20090061237A1

公开(公告)日：2009-03-05

申请号：US11846182

申请日：2007-08-28

申请人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

发明人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

IPC分类号： B32B27/06 ,  C08G77/00 ,  C08G77/12

CPC分类号： C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02359 ,  H01L21/3105

摘要： A porous SiCOH (e.g., p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The inventive p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bondings as compared to prior art p-SiCOH dielectric films. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking —(CHx)— chains wherein x is 1,2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond.

摘要翻译： 通过在不饱和烃环境中后处理使多孔SiCOH（例如，p-SiCOH）介电膜在其中由增加的四面体应变引起的应力变化最小化。 与现有技术的p-SiCOH介电膜相比，本发明的p-SiCOH电介质膜具有更多的（（CH x））和更少的Si-O-H和Si-H键。 此外，提供稳定的pSiOCH电介质膜，其中至少在孔内的Si-OH（硅烷醇）和Si-H基团的量通过后处理减少约90％以下。 因此，与现有技术的p-SiCOH介电膜相比，本发明的p-SiCOH介电膜具有疏水性改善。 在本发明中，由于本发明薄膜的孔包括其中x为1,2或3的稳定的交联 - （CHx） - 链，因此制备柔性的p-SiCOH介电膜。 介电膜是利用包括至少一个C-C双键和/或至少一个C-C三键的气态环境的退火步骤进行的。

公开(公告)号：US20080265415A1

公开(公告)日：2008-10-30

申请号：US12164599

申请日：2008-06-30

申请人： Matthew E. Colburn ,  Stephen M. Gates ,  Jeffrey C. Hedrick ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian

发明人： Matthew E. Colburn ,  Stephen M. Gates ,  Jeffrey C. Hedrick ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian

IPC分类号： H01L23/52

CPC分类号： H05K3/0079 ,  H01L21/0331 ,  H01L21/76849 ,  H05K3/282 ,  H05K2203/1173 ,  Y10T428/24802

摘要： A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.