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163 条记录 (耗时 0.037 秒)

    Semitubular metal-oxide-semiconductor field effect transistor
    41.
    发明授权
    Semitubular metal-oxide-semiconductor field effect transistor 有权
    半金属氧化物半导体场效应晶体管

    公开(公告)号：US07868374B2

    公开(公告)日：2011-01-11

    申请号：US12034899

    申请日：2008-02-21

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

    IPC分类号： H01L29/788

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7853

    摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.

    摘要翻译： 在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。 去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。 在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。 半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

    FLASH MEMORY GATE STRUCTURE FOR WIDENED LITHOGRAPHY WINDOW
    44.
    发明申请
    FLASH MEMORY GATE STRUCTURE FOR WIDENED LITHOGRAPHY WINDOW 失效
    闪存光栅窗口的闪存存储器门结构

    公开(公告)号：US20100052034A1

    公开(公告)日：2010-03-04

    申请号：US12198345

    申请日：2008-08-26

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.

    摘要翻译： 属于闪存器件区域的半导体衬底的第一部分凹陷到凹陷深度以形成凹陷区域，而属于逻辑器件区域的半导体衬底的第二部分被掩蔽层保护。 形成在凹陷区域内的第一栅介质层和第一栅极导体层，使得第一栅极导电层与浅沟槽隔离结构的顶表面基本共面。 随后对第二栅介质层，第二栅极导体层和栅帽硬掩模层进行构图，每个具有平坦的顶表面。 闪存器件区域中的栅极结构的图案被转移到第一栅极导体层和第一栅极介电层中，以分别形成浮置栅极和第一栅极电介质。

    Method of fabrication of interconnect structures
    46.
    发明授权
    Method of fabrication of interconnect structures 失效
    互连结构的制造方法

    公开(公告)号：US07563710B2

    公开(公告)日：2009-07-21

    申请号：US11860602

    申请日：2007-09-25

    申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

    发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a damascene wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor.

    摘要翻译： 一种形成镶嵌线的方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。

    MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SiCOH DIELECTRICS
    48.
    发明申请
    MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SiCOH DIELECTRICS 有权
    用于SiCOH电介质的无损伤双面加工的多层HARDMASK方案

    公开(公告)号：US20080311744A1

    公开(公告)日：2008-12-18

    申请号：US12198602

    申请日：2008-08-26

    申请人： Nicholas C.M. Fuller ,  Stephen McConnell Gates ,  Timothy J. Dalton

    发明人： Nicholas C.M. Fuller ,  Stephen McConnell Gates ,  Timothy J. Dalton

    IPC分类号： H01L21/768

    CPC分类号： H01L21/0331 ,  H01L21/76811 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/31667 ,  H01L2924/00

    摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

    摘要翻译： 具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。 本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。 后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

    ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST
    49.
    发明申请
    ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST 有权
    添加沉积物中的多氯硅烷蚀刻阻垢剂

    公开(公告)号：US20080286972A1

    公开(公告)日：2008-11-20

    申请号：US12170634

    申请日：2008-07-10

    申请人： Timothy J. Dalton ,  Wesley C. Natzle ,  Paul W. Pastel ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

    发明人： Timothy J. Dalton ,  Wesley C. Natzle ,  Paul W. Pastel ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

    IPC分类号： H01L21/308

    CPC分类号： H01L21/32139 ,  H01L21/32137 ,  Y10S438/909

    摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.

    摘要翻译： 一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。 使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。 压载气体可以类似于或等同于在处理室内产生的气态副产物。 压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。 这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。 当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。 钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。