公开(公告)号：US09634083B2

公开(公告)日：2017-04-25

申请号：US13710382

申请日：2012-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen

IPC: H01L21/20 ,  H01L29/06 ,  H01L21/441 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/441 ,  H01L29/0603 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures.

公开(公告)号：US09570578B2

公开(公告)日：2017-02-14

申请号：US14619085

申请日：2015-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Chien-Liang Lin ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/28 ,  H01L29/49 ,  H01L21/322 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28506 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/517

Abstract: A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors.

Abstract translation: 门形成工艺包括以下步骤。 在基板上形成栅极电介质层。 在栅介质层上形成阻挡层。 硅晶种层和硅层依次直接形成在阻挡层上，其中硅晶种层和硅层由不同的前体形成。

公开(公告)号：US09543408B1

公开(公告)日：2017-01-10

申请号：US14835730

申请日：2015-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Hui Lin ,  Keng-Jen Lin ,  Chun-Yao Yang ,  Yu-Ren Wang

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/3215

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/32155 ,  H01L21/324 ,  H01L23/544 ,  H01L29/66795 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.

Abstract translation: 形成图案化掩模掩模层的方法包括以下步骤。 提供半导体衬底。 在半导体衬底上形成非晶硅层。 对非晶硅层进行注入工艺。 在植入处理之后对非晶硅层进行退火处理。 在退火处理之后，在非晶硅层上形成图案化的硬掩模层。

公开(公告)号：US09514993B2

公开(公告)日：2016-12-06

申请号：US14664933

申请日：2015-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Ted Ming-Lang Guo ,  Hsu Ting ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L21/283 ,  H01L21/308

CPC classification number: H01L21/823814 ,  H01L21/02236 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823878

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构彼此互补。 接下来，形成覆盖第二栅极结构的第一掩模层，随后在第一晶体管的两个相应的两侧在衬底中形成第一凹槽。 然后，形成第一凹部，在每个第一凹部中形成第一外延层。 在形成第一外延层之后，在第一外延层上形成局部保护帽，然后除去第一掩模层。

公开(公告)号：US20160314969A1

公开(公告)日：2016-10-27

申请号：US15166291

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuang-Hsiu Chen ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/02636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, next, a first dry etching process is performed, to form a recess in the substrate. Afterwards, an ion implantation process is performed to a bottom surface of the recess, a wet etching process is then performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively, and a second dry etching process is performed, to etch partial bottom surface of the recess, wherein after the second dry etching process is performed, a lower portion of the recess has a U-shaped cross section profile.

Abstract translation: 本发明提供一种形成半导体结构的方法，包括：首先提供衬底，然后进行第一干蚀刻工艺，以在衬底中形成凹陷。 之后，对凹部的底面执行离子注入工艺，然后执行湿蚀刻工艺，以蚀刻凹部的部分侧壁，从而分别在凹槽的两侧形成至少两个尖端，并且 进行第二干蚀刻工艺，以蚀刻凹部的部分底表面，其中在执行第二干蚀刻工艺之后，凹部的下部具有U形横截面轮廓。

公开(公告)号：US20160284601A1

公开(公告)日：2016-09-29

申请号：US14664933

申请日：2015-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Ted Ming-Lang Guo ,  Hsu Ting ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/283

CPC classification number: H01L21/823814 ,  H01L21/02236 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823878

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构彼此互补。 接下来，形成覆盖第二栅极结构的第一掩模层，随后在第一晶体管的两个相应的两侧在衬底中形成第一凹槽。 然后，形成第一凹部，在每个第一凹部中形成第一外延层。 在形成第一外延层之后，在第一外延层上形成局部保护帽，然后除去第一掩模层。

公开(公告)号：US09419089B1

公开(公告)日：2016-08-16

申请号：US14714361

申请日：2015-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuang-Hsiu Chen ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/225 ,  H01L21/283

CPC classification number: H01L21/02636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present invention provides a semiconductor structure, which includes a substrate, at least two gate structures disposed on the substrate, a first recess, disposed in the substrate between two gate structures, the first recess having a U-shaped cross section profile, and a second recess, disposed on the first recess, the second recess having a polygonal shaped cross section profile, and has at least two tips on two sides of the second recess, the first recess and the second recess forming an epitaxial recess.

Abstract translation: 本发明提供了一种半导体结构，其包括基板，设置在基板上的至少两个栅极结构，设置在两个栅极结构之间的基板中的第一凹部，第一凹部具有U形横截面轮廓，以及 第二凹部，设置在第一凹部上，第二凹部具有多边形截面轮廓，并且在第二凹部的两侧具有至少两个尖端，第一凹部和第二凹部形成外延凹部。

公开(公告)号：US20160133474A1

公开(公告)日：2016-05-12

申请号：US14537827

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Feng Ku ,  Shao-Wei Wang ,  Yi-Hui Lin ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/28035

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，其中栅极结构包括高k电介质层; 通过注入第一气体将栅极结构周围的环境压力增加到预定压力; 将环境压力降低到基础压力; 以及在所述栅极结构周围形成间隔物。

公开(公告)号：US09330902B1

公开(公告)日：2016-05-03

申请号：US14731227

申请日：2015-06-04

Applicant: United Microelectronics Corp.

Inventor： Tsai-Yu Wen ,  Shih-Cheng Chen ,  Shan Ye ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/3205 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7836

Abstract: A method for forming a HfOx film based on atomic layer deposition (ALD) process includes: providing a substrate; dividing a plurality of ALD cycles as needed into multiple depositing stages, wherein each of the ALD cycles includes applying HfCl4 pulse and applying H2O pulse over the substrate and a content ratio of HfCl4 to H2O is different and increasing for the depositing stages; and performing the depositing stages to form a HfOx film.

Abstract translation: 基于原子层沉积（ALD）工艺形成HfO x膜的方法包括：提供衬底; 根据需要将多个ALD循环分成多个沉积阶段，其中每个ALD循环包括施加HfCl 4脉冲并在衬底上施加H 2 O脉冲，并且HfCl 4与H 2 O的含量比不同并且对于沉积阶段而言增加; 并进行沉积阶段以形成HfO x膜。

公开(公告)号：US09130014B2

公开(公告)日：2015-09-08

申请号：US14085811

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Tsuo-Wen Lu ,  Wei-Jen Chen ,  Chih-Chung Chen

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76237 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/32105 ,  H01L21/76205 ,  H01L21/76224

Abstract: A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.

Abstract translation: 公开了一种用于制造浅沟槽隔离结构的方法。 该方法包括以下步骤：（a）提供衬底; （b）在衬底中形成沟槽; （c）在沟槽中形成硅层; 和（d）进行氧化处理以将硅层的表面部分地转变为氧化物层。