公开(公告)号：US20170221796A1

公开(公告)日：2017-08-03

申请号：US15011433

申请日：2016-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu

IPC: H01L23/48 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A TSV structure includes a substrate comprising at least a TSV opening formed therein, a conductive layer disposed in the TSV opening, and a bi-layered liner disposed in between the substrate and the conductive layer. More important, the bi-layered liner includes a first liner and a second liner, and a Young's modulus of the first liner is different from a Young's modulus of the second liner.

公开(公告)号：US20170186668A1

公开(公告)日：2017-06-29

申请号：US14982565

申请日：2015-12-29

Applicant: United Microelectronics Corp.

Inventor： Kuei-Sheng Wu ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2225/06541

Abstract: A method for is used for forming a semiconductor device having a through-substrate via. The method includes providing a preliminary structure having an ILD layer on a substrate and a buffer layer on the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.

公开(公告)号：US09478496B1

公开(公告)日：2016-10-25

申请号：US14945410

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin

IPC: H01L21/30 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/24 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/24105 ,  H01L2224/24147 ,  H01L2224/80097 ,  H01L2224/80896 ,  H01L2224/83896 ,  H01L2224/9205 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2224/8203 ,  H01L2224/821

Abstract: A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the second wafer. A plurality of first interconnects are disposed within the he first bonding layer. A plurality of second interconnects are disposed within the second bonding layer. An interface is disposed between the first bonding layer and the second bonding layer. At least a through silicon via penetrates the first wafer, the first bonding layer and the interface to enter the second bonding layer. The through silicon via contacts one of the first interconnects and one of the second interconnects.

Abstract translation: 晶片到晶片结构包括第一晶片，第二晶片。 第一接合层和第二接合层设置在第一晶片和第二晶片之间。 多个第一互连设置在第一粘合层内。 多个第二互连设置在第二接合层内。 接口设置在第一接合层和第二接合层之间。 至少穿透硅通孔穿透第一晶片，第一结合层和界面以进入第二结合层。 贯穿硅通孔接触第一互连中的一个和第二互连中的一个。

公开(公告)号：US09287173B2

公开(公告)日：2016-03-15

申请号：US13900565

申请日：2013-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

Abstract translation: 透硅通孔包括基底和导电塞。 基板在一侧具有孔。 导电插头设置在孔中，导电插头具有从侧面突出的上部，其中上部具有顶部和底部，并且顶部比底部更细。 此外，还提供了通过硅通孔形成的贯穿硅通孔工艺，其包括以下步骤。 从一侧在基板上形成孔。 形成第一导电材料以覆盖孔和侧面。 形成图案化的光致抗蚀剂以覆盖侧面但暴露孔。 在暴露的第一导电材料上形成第二导电材料。 去除图案化的光致抗蚀剂。 去除侧面上的第一导电材料以在孔中形成导电塞。

公开(公告)号：US20150332996A1

公开(公告)日：2015-11-19

申请号：US14280680

申请日：2014-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Kuei-Sheng Wu ,  Ming-Tse Lin ,  Chung-Sung Chiang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  G03F7/20

CPC classification number: H01L21/486 ,  G03F7/203 ,  G03F7/38 ,  G03F7/70 ,  H01L21/48 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1701 ,  H05K3/0082 ,  H05K2201/10378

Abstract: The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically.

Abstract translation: 本发明提供一种包括多个电路设计和设置在电路设计上的最上层电路设计的插入器。 最大曝光区域被定义为可以通过光刻扫描器的单次射击来定义的最大尺寸。 电路设计的最小电路设计尺寸小于最大曝光区域的尺寸。 因此，电路设计分别仅由光刻扫描器的单个镜头形成。 最上面的电路设计的长度大于最大曝光区域的长度，因此电路设计是通过光刻地拼接两个光掩模形成的。

公开(公告)号：US20150014828A1

公开(公告)日：2015-01-15

申请号：US13939184

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chia-Fang Lin

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L23/481 ,  H01L23/535 ,  H01L23/585 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.

Abstract translation: 本发明提供一种具有屏蔽结构的半导体器件。 半导体器件包括衬底，RF电路，屏蔽结构和互连系统。 基板包括有源侧和背面。 RF电路设置在基板的有源侧。 屏蔽结构设置在有源侧并且包围RF电路。 屏蔽结构接地。 屏蔽结构包括不穿透基板的屏蔽TST。 互连系统设置在基板的有源侧。 互连系统包括将信号电连接到RF电路的连接单元。

公开(公告)号：US20140145326A1

公开(公告)日：2014-05-29

申请号：US13689727

申请日：2012-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract translation: 提出了具有集成无源器件的基板及其制造方法。 衬底可以包括通过硅通孔，具有第一无源器件图案和堆叠通孔的至少一个再分布层，以及具有第二无源器件图案的下凸块金属层。

公开(公告)号：US11557558B2

公开(公告)日：2023-01-17

申请号：US16984601

申请日：2020-08-04

Applicant: United Microelectronics Corp.

Inventor： Zhirui Sheng ,  Hui-Ling Chen ,  Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Chien En Hsu

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

公开(公告)号：US11450633B2

公开(公告)日：2022-09-20

申请号：US16781937

申请日：2020-02-04

Applicant: United Microelectronics Corp.

Inventor： Ming-Tse Lin ,  Chung-Hsing Kuo ,  Hui-Ling Chen

IPC: H01L23/00

Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.

公开(公告)号：US11164822B1

公开(公告)日：2021-11-02

申请号：US17035385

申请日：2020-09-28

Applicant: United Microelectronics Corp.

Inventor： Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Hui-Ling Chen ,  Chien-Ming Lai

IPC: H01L23/544 ,  H01L23/488 ,  H01L23/00

Abstract: A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.