公开(公告)号：US20130015496A1

公开(公告)日：2013-01-17

申请号：US13544339

申请日：2012-07-09

申请人： Akitoyo Konno ,  Katsunori Azuma ,  Takashi Ando

发明人： Akitoyo Konno ,  Katsunori Azuma ,  Takashi Ando

IPC分类号： H01L25/16

CPC分类号： H01L23/49 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/49 ,  H01L25/072 ,  H01L29/417 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2924/00014

摘要： A power semiconductor device is provided in which reliability can be improved when the parallel number of semiconductor devices increases. When a bonding face on collector electrode is on an upper side, and a bonding face on emitter electrode is on a lower side, a collector electrode joint region as a joint region between a collector trace and a collector electrode on a chip mounted substrate and an emitter electrode joint region as a joint region between an emitter trace and an emitter electrode are located at a same position in an up-and-down direction and are adjacent in a right-and-left direction at an interval of 2 mm or more and 4 mm or less.

摘要翻译： 提供一种功率半导体器件，其中当半导体器件的平行数量增加时可以提高可靠性。 当集电极上的接合面在上侧，发射电极的接合面位于下侧时，集电极接合区域作为芯片安装基板上的集电体迹线与集电极之间的接合区域， 作为发射极和发射极之间的接合区域的发射极电极接合区域位于上下方向的相同位置，并且在左右方向上以2mm以上的间隔相邻， 4毫米或更小。

公开(公告)号：US20120299123A1

公开(公告)日：2012-11-29

申请号：US13570388

申请日：2012-08-09

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US08317081B2

公开(公告)日：2012-11-27

申请号：US12907406

申请日：2010-10-19

申请人： Shogo Ogaki ,  Takashi Ando ,  Masaru Inoue

发明人： Shogo Ogaki ,  Takashi Ando ,  Masaru Inoue

IPC分类号： B23K31/02

CPC分类号： B23K3/04 ,  B23K1/0016 ,  G11B5/4833

摘要： A reflow bonding method easily bonds first and second wiring members together by reflowing solder arranged on at least one of first and second bonding parts that are defined on the first and second wiring members, respectively. The method includes positioning the first and second wiring members so that the first and second bonding parts face each other with the solder interposed between them and heating and pressing one of the first and second bonding parts from behind with a pressing face of a heater chip so that the first and second bonding parts lie one on another and so that the solder is heated and reflows to bond the first and second wiring members together.

摘要翻译： 回流焊接方法通过分别在第一和第二布线构件上限定的第一和第二接合部中的至少一个上的回流焊料容易地将第一和第二布线构件接合在一起。 该方法包括：定位第一和第二布线构件，使得第一和第二接合部分彼此面对，并且夹在它们之间的焊料并且用加热器片的按压面从后面加热和加压第一和第二接合部分中的一个，从而 第一和第二接合部分彼此位于一起并且使得焊料被加热并且回流以将第一和第二配线构件结合在一起。

公开(公告)号：US08288836B2

公开(公告)日：2012-10-16

申请号：US12244889

申请日：2008-10-03

申请人： Itaru Oshiyama ,  Takashi Ando ,  Susumu Hiyama ,  Tetsuji Yamaguchi ,  Yuko Ohgishi ,  Harumi Ikeda

发明人： Itaru Oshiyama ,  Takashi Ando ,  Susumu Hiyama ,  Tetsuji Yamaguchi ,  Yuko Ohgishi ,  Harumi Ikeda

IPC分类号： H01L31/02

CPC分类号： H01L27/14636 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14818 ,  H01L27/14868

摘要： A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section.

摘要翻译： 具有执行入射光的光电转换的光感测部的固态成像装置包括：形成在感光部的受光面上的绝缘层; 在绝缘层上形成具有负电荷的层; 以及形成在光检测部的光接收表面上的空穴积聚层。

公开(公告)号：US08274116B2

公开(公告)日：2012-09-25

申请号：US12619209

申请日：2009-11-16

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

摘要翻译： 用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。 栅极堆叠包括形成在半导体衬底上的锗（Ge）材料层，形成在Ge材料层上的扩散阻挡层，在扩散阻挡层上形成的具有大于约3.9的高介电常数的高k电介质，以及 形成在高k电介质层上方的导电电极层。

公开(公告)号：US20120181630A1

公开(公告)日：2012-07-19

申请号：US13006656

申请日：2011-01-14

申请人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

发明人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

公开(公告)号：US20120147241A1

公开(公告)日：2012-06-14

申请号：US13402298

申请日：2012-02-22

申请人： Tetsuji Yamaguchi ,  Yasushi Maruyama ,  Takashi Ando ,  Susumu Hiyama ,  Yuko Ohgishi

发明人： Tetsuji Yamaguchi ,  Yasushi Maruyama ,  Takashi Ando ,  Susumu Hiyama ,  Yuko Ohgishi

IPC分类号： H04N5/335 ,  H01L27/148

CPC分类号： H01L27/14609 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/022466 ,  H01L31/022475

摘要： A solid-state imaging device includes a substrate with oppositely facing first surface and second surfaces, light being received through the second surface; a wiring layer on the first surface; a photodetector in the substrate; a charge accummulation region between the second surface and the photodetector; and an insulating layer over the second surface, the insulating layer have a region that is at least partially crystallized.

摘要翻译： 固态成像装置包括具有相对面对的第一表面和第二表面的基板，光被接收通过第二表面; 第一表面上的布线层; 基板上的光电检测器; 所述第二表面和所述光电检测器之间的电荷累积区域; 以及在所述第二表面上的绝缘层，所述绝缘层具有至少部分地结晶的区域。

公开(公告)号：US20120083121A1

公开(公告)日：2012-04-05

申请号：US13012879

申请日：2011-01-25

申请人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

发明人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

IPC分类号： H01L21/463

CPC分类号： H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

摘要： Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

摘要翻译： 用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。 采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

公开(公告)号：US20110309455A1

公开(公告)日：2011-12-22

申请号：US12816605

申请日：2010-06-16

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US07989902B2

公开(公告)日：2011-08-02

申请号：US12487248

申请日：2009-06-18

申请人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Vijay Narayanan

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

摘要翻译： 高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。 清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属 每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。 符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。 此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。 结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。