公开(公告)号：US20160308537A1

公开(公告)日：2016-10-20

申请号：US15037500

申请日：2013-11-22

Applicant: FREESCALE SEMICONDUCTOR,INC.

Inventor： Birama Goumballa ,  Cristian Pavao-Moreira ,  Yi Yin

IPC: H03L1/02 ,  H03K5/24 ,  G05F1/56 ,  H03K3/037

CPC classification number: H03L1/023 ,  G01K1/02 ,  G01K7/01 ,  G01K7/16 ,  G05F1/561 ,  G05F3/30 ,  H03K3/011 ,  H03K3/0377 ,  H03K5/24 ,  H03L1/022

Abstract: A current-to-voltage converter receives a current which varies with temperature according to a selected one of two or more temperature coefficient factors and converts it to a temperature-dependent voltage to be used as a control signal to a varactor in a voltage controlled oscillator, VCO, to compensate for temperature-induced frequency drift in the VCO. A feedback arrangement with hysteresis is provided for controlling the selection of the temperature coefficient factor and operates by comparing the temperature-dependent voltage with a reference voltage. The reference voltage may be pre-set and equivalent to a known operating temperature. A switching signal is generated when Vout approaches the reference voltage and in response a control module generates a selection signal for selecting a different temperature coefficient factor. Thus multi-slope voltage and current generation with a wide dynamic range is continuously provided, which is particularly useful for controlling VCO's used in short range FMCW radar systems.

Abstract translation: 电流 - 电压转换器接收根据两个或多个温度系数因子中选择的一个温度变化的电流，并将其转换为温度相关电压，以用作控制信号到压控振荡器中的变容二极管 ，VCO，以补偿VCO中的温度感应频率漂移。 提供具有迟滞的反馈装置，用于控制温度系数因子的选择，并通过将温度依赖电压与参考电压进行比较来进行操作。 参考电压可以被预先设定并且等于已知的工作温度。 当Vout接近参考电压时产生开关信号，并且响应于控制模块产生用于选择不同的温度系数因子的选择信号。 因此，连续提供具有宽动态范围的多斜坡电压和电流产生，这对于控制在短距离FMCW雷达系统中使用的VCO特别有用。

公开(公告)号：US09473396B1

公开(公告)日：2016-10-18

申请号：US14704988

申请日：2015-05-06

Applicant: Satya Srinivasa Murthy Nittala ,  Srinivasa R. Addepalli ,  Balaji Padnala

Inventor： Satya Srinivasa Murthy Nittala ,  Srinivasa R. Addepalli ,  Balaji Padnala

IPC: H04L12/28 ,  H04L12/721 ,  H04L12/46

CPC classification number: H04L45/38 ,  H04L12/4641 ,  H04L45/566

Abstract: A system for steering data packets in a communication network that includes compute nodes having processors for executing application and service virtual machines (VMs), and traffic steering accelerators. A virtual local area network-identifier (VLAN-ID) assignment module generates records and associates the records with the service VMs. Each record includes an input VLAN-ID, an output VLAN-ID, and a port number corresponding to one of the service VMs. A service-chaining module generates chaining rules associated with n-Tuples. A traffic steering controller generates a chain of the records based on the service chaining rules. The traffic steering accelerator then steers the data packets based on the input and output VLAN-IDs included in the data packet.

Abstract translation: 一种用于在通信网络中指导数据分组的系统，其包括具有用于执行应用和服务虚拟机（VM）的处理器的计算节点和业务转向加速器。 虚拟局域网标识符（VLAN-ID）分配模块生成记录并将记录与服务VM关联起来。 每个记录包括输入VLAN-ID，输出VLAN-ID和与其中一个服务VM相对应的端口号。 服务链模块生成与n元组相关联的链接规则。 交通转向控制器基于服务链规则生成记录链。 然后，流量转向加速器基于包括在数据分组中的输入和输出VLAN-ID来引导数据分组。

公开(公告)号：US09472528B2

公开(公告)日：2016-10-18

申请号：US14296835

申请日：2014-06-05

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Weng F. Yap

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/49 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An integrated electronic package includes an integrated circuit (IC) die and conductive discrete components. Electrical interconnects are formed directly between bond pads on an active side of the IC die and contacts on the conductive discrete components without an intervening lead frame. The IC die, conductive discrete components and electrical interconnects are embedded in an encapsulation material. Contact surfaces of at least some of the conductive discrete components are exposed from the encapsulation material and can be attached to a printed circuit board in order to mount the integrated electronic package to the printed circuit board.

Abstract translation: 集成电子封装包括集成电路（IC）裸片和导电分立组件。 电互连直接形成在IC芯片的有源侧的接合焊盘和导电分立元件之间的接触处，而没有中间引线框架。 IC芯片，导电分立元件和电气互连嵌入在封装材料中。 至少一些导电分立组件的接触表面从封装材料露出并且可以附着到印刷电路板上，以便将集成电子封装安装到印刷电路板上。

公开(公告)号：US20160299859A1

公开(公告)日：2016-10-13

申请号：US15036847

申请日：2013-11-22

Applicant: Daniel Dumitru Popa ,  ALEXANDRA DRACEA ,  DRAGOS MILOIU

Inventor： Daniel Dumitru Popa ,  ALEXANDRA DRACEA ,  DRAGOS MILOIU

IPC: G06F13/28 ,  G06F11/36 ,  G06F3/0484

CPC classification number: G06F13/28 ,  G06F3/0484 ,  G06F11/3648

Abstract: There is disclosed an apparatus for external access to core resources (211,212) of a processor (2) comprising a processing core (21), a shared memory (22), and a multiple paths Direct Memory Access, DMA, controller (23). Access to core critical resources can be performed while the core is executing an application program. The proposed apparatus comprises a Manager module (13) which is operable to setup the DMA controller to copy the assigned core resources via allocated DMA channel into a safe memory region. Further, an Observer module (14) is operable to read the transferred data and make the correlation on the host apparatus side. This allows accessing data used by the core via the DMA controller into, e.g., a run-time debugger accessible region.

Abstract translation: 公开了一种用于外部访问包括处理核心（21），共享存储器（22）和多路径直接存储器访问（DMA）控制器（23）的处理器（2）的核心资源（211,212）的装置。 当核心执行应用程序时，可以执行对核心关键资源的访问。 所提出的装置包括管理器模块（13），其可操作以设置DMA控制器，以通过分配的DMA通道将分配的核心资源复制到安全存储器区域中。 此外，观察者模块（14）可操作以读取所传送的数据并在主机设备侧进行相关。 这允许将核心经由DMA控制器使用的数据访问到例如运行时调试器可访问区域中。

公开(公告)号：US09467181B2

公开(公告)日：2016-10-11

申请号：US14710828

申请日：2015-05-13

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Andrei-Alexandru Enescu ,  Anton Antal

IPC: H04B1/00 ,  H04B1/12 ,  H04B1/10

CPC classification number: H04B1/123 ,  H04B1/1036

Abstract: The present application suggests a receiver and a method of operating thereof for determining a noise estimate based on a radio frequency signal from an interference source over different propagation paths through a plurality of antennas. A covariance matrix estimator coupled through separate processing paths to a respective one of the plurality of antennas is arranged to determine an estimate of a covariance matrix based on the received radio frequency signal. A noise estimator coupled to the covariance matrix estimator for receiving the estimate of the covariance matrix is arranged to determine a noise estimate by solving a polynomial equation of second order as a function of the noise estimate on the basis the elements of the covariance matrix estimate relating to a set of two antennas.

Abstract translation: 本申请提出了一种接收机及其操作方法，用于基于来自干扰源的射频信号，通过多个天线在不同的传播路径上确定噪声估计。 通过分离的处理路径耦合到多个天线中的相应一个天线的协方差矩阵估计器被布置为基于所接收的射频信号来确定协方差矩阵的估计。 耦合到用于接收协方差矩阵的估计的协方差矩阵估计器的噪声估计器被布置成通过基于协方差矩阵估计相关的元素求解作为噪声估计的函数的二阶多项式方程来确定噪声估计 到一组两个天线。

公开(公告)号：US20160293526A1

公开(公告)日：2016-10-06

申请号：US14887304

申请日：2015-10-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Zhijie Wang ,  Zhigang Bai ,  You Ge ,  Meng Kong Lye

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2224/75981 ,  H01L2224/78981 ,  H01L2224/83447 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A packaged integrated circuit (IC) device having a heatsink mounted onto an IC die, itself mounted onto a die pad, is assembled using a lead frame having tie bars that deflect during an encapsulation phase of the device assembly, which enables the die pad, the die, and the heatsink to move relative to the lead frame support structure when compressive force is applied by the molding tool. This movement results in negligible relative displacement between the heatsink and the die during encapsulation, which reduces the probability of physical damage to the die. Each tie bar has a number of differently angled sections that enable it to deflect when compressive force is applied to it.

Abstract translation: 具有安装在IC芯片上的散热片的封装集成电路（IC）装置，其本身安装在芯片焊盘上，使用引线框来组装，该引线框架具有在器件组件的封装阶段期间偏转的连接杆， 模具和散热器当通过模制工具施加压力时相对于引线框架支撑结构移动。 这种移动在封装期间导致散热器和管芯之间的相对位移可以忽略不计，这降低了对模具的物理损伤的可能性。 每个连杆具有多个不同角度的部分，使得当压缩力施加到其上时它能够偏转。

公开(公告)号：US09462556B2

公开(公告)日：2016-10-04

申请号：US13582769

申请日：2010-03-22

Applicant: Michael Priel ,  Dan Kuzmin ,  Anton Rozen

Inventor： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC: G06F9/00 ,  G06F1/32 ,  H04W52/02

CPC classification number: H04W52/0261 ,  G06F1/32 ,  G06F9/00 ,  Y02D70/00

Abstract: An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.

Abstract translation: 集成电路装置包括信号处理系统，该信号处理系统具有通过第一生产过程制造的至少一个第一信号处理模块; 以及通过第二生产过程制造的至少一个第二信号处理模块，其中第二生产过程与第一生产过程不同。 信号处理系统还包括信号处理管理模块，其被布置成：确定集成电路装置的期望的系统性能; 确定信号处理系统的至少一个操作条件; 并且至少部分地基于：确定的期望系统性能来配置所述信号处理系统的信号处理操作模式; 所述至少一个确定的操作条件; 以及第一生产过程和第二生产过程中的至少一个。

公开(公告)号：US20160285261A1

公开(公告)日：2016-09-29

申请号：US14836048

申请日：2015-08-26

Applicant: JEAN PHILIPPE LAINE ,  PATRICE BESSE

Inventor： JEAN PHILIPPE LAINE ,  PATRICE BESSE

IPC: H02H9/04 ,  H01L21/8222 ,  H01L29/10 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L21/8222 ,  H01L27/0262 ,  H01L29/1095

Abstract: An electrostatic discharge (ESD) device is disclosed having two PNP transistors. During a high-voltage ESD event a parasitic NPN transistor couples to one of the two PNP transistors to provide ESD protection.

Abstract translation: 公开了具有两个PNP晶体管的静电放电（ESD）器件。 在高电压ESD事件期间，寄生NPN晶体管耦合到两个PNP晶体管之一以提供ESD保护。

公开(公告)号：US20160282896A1

公开(公告)日：2016-09-29

申请号：US14671564

申请日：2015-03-27

Applicant: William E. Edwards ,  Anthony F. Andresen

Inventor： William E. Edwards ,  Anthony F. Andresen

IPC: G05F5/00

CPC classification number: G05F5/00

Abstract: A method of undervoltage detection includes detecting a voltage level for a power supply of a system, placing the system in an undervoltage state if the voltage level is below an undervoltage threshold, activating a load of the system at a first power level if the detected voltage level exceeds a first activation threshold and if the system resides in the undervoltage state, and activating the load at a second power level if the detected voltage level exceeds a second activation threshold.

Abstract translation: 一种欠压检测方法包括：检测系统电源的电压电平，如果电压低于欠电压阈值，则使系统处于欠电压状态，如果检测到的电压，则启动系统的负载 电平超过第一激活阈值，并且如果系统处于欠电压状态，并且如果检测到的电压电平超过第二激活阈值，则以第二功率电平激活负载。

公开(公告)号：US09455233B1

公开(公告)日：2016-09-27

申请号：US14956406

申请日：2015-12-02

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Rishi Bhooshan ,  Mohit Arora ,  Rakesh Pandey

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/573 ,  G06F21/87 ,  H01L23/576 ,  H01L23/585

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh and an active wire mesh. The wire meshes can be formed in the same layer over the circuits to be protected or in different layers. The wire meshes also may cover the entire chip area or only predetermined areas, such as over secure memory and register areas. The wire meshes are connected to a tamper detection module, which monitors the meshes and any signals transmitted via the meshes to detect attempts to access the protected circuits via micro-probing.

Abstract translation: 用于产生表示篡改集成电路（IC）的一个或多个电路的篡改检测信号的系统包括静态金属丝网和活动金属丝网。 线网可以在要保护的电路或不同层中的相同层中形成。 线网也可以覆盖整个芯片区域或仅覆盖预定区域，例如过度安全的存储器和寄存器区域。 线网连接到篡改检测模块，该模块监控网格和通过网格传输的任何信号，以检测通过微探测访问受保护电路的尝试。