公开(公告)号：US20190190476A1

公开(公告)日：2019-06-20

申请号：US16223297

申请日：2018-12-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Satoshi TANAKA ,  Yasuhisa YAMAMOTO ,  Takayuki TSUTSUI ,  Isao OBU

IPC: H03G3/30 ,  H03F3/21 ,  H03F1/02 ,  H03F3/195

CPC classification number: H03G3/3042 ,  H03F1/0211 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/54 ,  H03F2203/21103 ,  H03F2203/21139 ,  H03G2201/106

Abstract: A power amplifier circuit includes a first transistor amplifying a first signal; a second transistor amplifying a second signal; a bias circuit supplying a bias current or voltage to a base or gate of the second transistor; and an attenuator attenuating the first or second signal in accordance with a control voltage supplied from the bias circuit. The attenuator includes a first diode to which the control voltage is supplied, a third transistor including a collector connected to a supply path of the first or second signal, an emitter connected to a ground, and a base to which the control voltage is supplied from the first diode, and a capacitor connected in parallel with the first diode. The control voltage decreases as a second signal power level increases. The third transistor allows part of the first or second signal to pass to the emitter in accordance with the control voltage.

公开(公告)号：US20190181805A1

公开(公告)日：2019-06-13

申请号：US16274016

申请日：2019-02-12

Applicant: NXP USA, Inc.

Inventor： Abdulrhman M. S. Ahmed ,  Mario M. Bokatius ,  Paul R. Hart ,  Joseph Staudinger ,  Richard E, Sweeney

IPC: H03F1/02 ,  H04L7/00 ,  H03F3/21 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  G06G7/10 ,  H03G1/00 ,  H04L27/22 ,  G06F13/42 ,  H03F3/19

CPC classification number: H03F1/0288 ,  G06F13/4282 ,  G06G7/10 ,  H03F3/189 ,  H03F3/19 ,  H03F3/211 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/387 ,  H03F2200/438 ,  H03F2200/451 ,  H03F2203/21106 ,  H03F2203/21193 ,  H03G1/0088 ,  H03G2201/106 ,  H04L7/0079 ,  H04L27/22

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

公开(公告)号：US20180358935A1

公开(公告)日：2018-12-13

申请号：US16104966

申请日：2018-08-20

Applicant: Texas Instruments Incorporated

Inventor： Shun QIAN ,  Kim Nordtorp MADSEN ,  Lucia WAN

IPC: H03F1/32 ,  H03F3/181 ,  H03F1/26 ,  H03G3/20 ,  H03F3/217

CPC classification number: H03F1/32 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/181 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/211 ,  H03F2200/471 ,  H03F2200/66 ,  H03G3/20 ,  H03G7/002 ,  H03G7/04 ,  H03G2201/106

Abstract: The disclosed embodiments include an audio amplifier system configured to provide a total harmonic distortion (THD) controlled clip detector and an automatic gain limiter (AGL) solution for a closed-loop amplifier. The audio amplifier system is capable of maintaining high power output without hard distortion (i.e., hard clipping) for providing better acoustics, while preventing damage to the system.

公开(公告)号：US20180337659A1

公开(公告)日：2018-11-22

申请号：US15532694

申请日：2014-12-03

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Fenghao MU ,  Sven MATTISSON

IPC: H03H11/24 ,  H03G1/00 ,  H04B1/40 ,  H04B7/06

CPC classification number: H03H11/245 ,  H03G1/0088 ,  H03G1/0094 ,  H03G2201/106 ,  H03H7/25 ,  H04B1/40 ,  H04B7/0608

Abstract: An attenuator for attenuating a signal is disclosed. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node. The attenuator further comprises a control circuit to generate control signals for controlling the first and second switched resistor networks.

公开(公告)号：US20180234059A1

公开(公告)日：2018-08-16

申请号：US15432767

申请日：2017-02-14

Applicant: General Electric Company

Inventor： Naresh Kesavan Rao ,  Krishnakumar Sundaresan ,  Nanette Judith Gruber ,  Bruno Hans Haider

IPC: H03F3/183 ,  H03G1/00 ,  H03F1/56 ,  A61B8/00 ,  A61B8/08

CPC classification number: H03F3/183 ,  A61B8/4444 ,  A61B8/4494 ,  A61B8/5269 ,  H03F1/56 ,  H03F2200/211 ,  H03F2200/222 ,  H03F2200/294 ,  H03G1/0088 ,  H03G2201/106

Abstract: A system including a low noise amplifier is provided. The system further includes a coarse attenuation circuit coupled to an input of the low noise amplifier and configurable to attenuate an input signal by a coarse attenuation interval. The system also includes a fine attenuation circuit coupled in feedback with the low noise amplifier and configurable to attenuate the input signal by a fine attenuation interval, wherein the fine attenuation interval is less than the coarse attenuation interval.

公开(公告)号：US20180212578A1

公开(公告)日：2018-07-26

申请号：US15926165

申请日：2018-03-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasushi OYAMA ,  Takayuki TSUTSUI ,  Kazuhito NAKAI

IPC: H03G1/00 ,  H03F3/72 ,  H03F3/24 ,  H03F3/19 ,  H03F3/213 ,  H03F1/56

CPC classification number: H03G1/0094 ,  H03F1/56 ,  H03F3/19 ,  H03F3/213 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/165 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2203/7209 ,  H03G2201/106 ,  H03G2201/40

Abstract: A power amplification module includes a first input terminal that receives a first transmit signal in a first frequency band, a second input terminal that receives a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band, a first amplification circuit that receives and amplifies the first transmit signal to produce a first amplified signal and outputs the first amplified signal, a second amplification circuit that receives and amplifies the second transmit signal to produce a second amplified signal and outputs the second amplified signal, a third amplification circuit that receives and amplifies the first or second amplified signal to produce an output signal and outputs the output signal, and an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a receive frequency band component of the second frequency band.

公开(公告)号：US20180123538A1

公开(公告)日：2018-05-03

申请号：US15583890

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jiang CHEN ,  Jeremy GOLDBLATT ,  Jose CABANILLAS

IPC: H03G3/30 ,  H03F3/193 ,  H03F3/21 ,  H03F1/56

CPC classification number: H03G3/3042 ,  H03F1/0266 ,  H03F1/223 ,  H03F1/32 ,  H03F1/56 ,  H03F3/189 ,  H03F3/193 ,  H03F3/21 ,  H03F3/245 ,  H03F3/45179 ,  H03F3/505 ,  H03F2200/102 ,  H03F2200/211 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/537 ,  H03F2200/69 ,  H03F2203/45394 ,  H03G2201/106

Abstract: A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor. The bias circuit stage includes one or more replica transistors that replicate transistors of the power amplifier or power amplifier core stage, an envelope detector replica transistor and a replica of the current source of the envelope detector circuit.

公开(公告)号：US20170359046A1

公开(公告)日：2017-12-14

申请号：US15618446

申请日：2017-06-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ken Wakaki ,  Daisuke Watanabe

IPC: H03G3/30 ,  H03F1/56 ,  H03F1/22

CPC classification number: H03G3/3042 ,  H03F1/223 ,  H03F1/56 ,  H03F3/193 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/61 ,  H03G1/0023 ,  H03G1/0035 ,  H03G1/0088 ,  H03G3/3052 ,  H03G2201/106

Abstract: An amplifier according to an embodiment of the present invention includes a first transistor and a second transistor that are connected between a ground point and a power supply. A control terminal of the first transistor is connected to an input terminal. A first terminal of the first transistor is connected to the ground point. A second terminal of the second transistor is connected to an output terminal. The amplifier further includes an impedance element and a variable resistance unit. The impedance element is connected between the second terminal of the second transistor and the power supply. The variable resistance unit is connected between the second terminal of the first transistor and the first terminal of the second transistor.

公开(公告)号：US20170264253A1

公开(公告)日：2017-09-14

申请号：US15516874

申请日：2014-07-09

Applicant: Oleksandr Gorbachov ,  Huan Zhao ,  Lisette L. Zhang ,  Lothar Musiol ,  Yongxi Qian

Inventor： Oleksandr Gorbachov ,  Huan Zhao ,  Lisette L. Zhang ,  Lothar Musiol ,  Yongxi Qian

IPC: H03F1/52 ,  H03G3/30 ,  H03F3/24 ,  H03F1/56 ,  H03F3/195

CPC classification number: H03F1/523 ,  H03F1/0266 ,  H03F1/56 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/105 ,  H03F2200/192 ,  H03F2200/204 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/405 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2200/78 ,  H03G3/3042 ,  H03G2201/106

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

公开(公告)号：US09602060B2

公开(公告)日：2017-03-21

申请号：US14327365

申请日：2014-07-09

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Oleksandr Gorbachov ,  Huan Zhao ,  Lisette L. Zhang ,  Lothar Musiol ,  Yongxi Qian

IPC: H03F3/19 ,  H03F1/02 ,  H03F3/21 ,  H03F1/52 ,  H03F1/56 ,  H03F3/195 ,  H03F3/24 ,  H03G3/30

CPC classification number: H03F1/523 ,  H03F1/0266 ,  H03F1/56 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/105 ,  H03F2200/192 ,  H03F2200/204 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/405 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2200/78 ,  H03G3/3042 ,  H03G2201/106

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.