公开(公告)号：US07425503B1

公开(公告)日：2008-09-16

申请号：US11486801

申请日：2006-07-14

申请人： Felix C. Li

发明人： Felix C. Li

IPC分类号： H01L29/74 ,  H01L29/417 ,  H01L31/111

CPC分类号： H01L24/83 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/29 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/83801 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18301 ,  H05K3/341 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01051 ,  H01L2924/3512 ,  H01L2924/00012

摘要： An apparatus and method for an enhanced thermally conductive package for high powered semiconductor devices. The package includes a semiconductor die having an active surface and a non-active surface and a metal layer formed on the non-active surface of the die. The package is intended to be mounted onto a metal pad provided on a printed circuit board. A solder is used to affix the metal layer on the non-active surface of the die to the metal pad of the printed circuit board. The interface between the die and the printed circuit board thus includes just three metal layers, including the non-active surface of the die, the solder, and the metal pad on the printed circuit board. The reduced number of metal layers improves heat dissipation and thermal conductivity of the package.

摘要翻译： 一种用于高功率半导体器件的增强导热封装的装置和方法。 该封装包括具有活性表面和非活性表面的半导体管芯以及形成在管芯的非活性表面上的金属层。 该封装旨在安装在设置在印刷电路板上的金属焊盘上。 使用焊料将金属层固定在印模电路板的金属焊盘上的裸片的非活性表面上。 因此，管芯和印刷电路板之间的界面仅包括三个金属层，包括管芯的非活性表面，焊料和印刷电路板上的金属焊盘。 减少数量的金属层改善了封装的散热和导热性。

公开(公告)号：US07417265B2

公开(公告)日：2008-08-26

申请号：US11345789

申请日：2006-02-03

申请人： Antonin Rozsypal

发明人： Antonin Rozsypal

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L29/872

摘要： In one embodiment, a Schottky diode structure comprises a Schottky barrier layer in contact with a semiconductor material through a Schottky contact opening. A conductive ring is formed adjacent the Schottky contact opening and is separated from the semiconductor material by a thin insulating layer. Another insulating layer is formed overlying the structure, and a contact opening is formed therein. The contact opening is wider than the Schottky contact opening and exposes portions of the conductive ring. A Schottky barrier metal is formed in contact with the semiconductor material through the Schottky contact opening, and is formed in further+contact with the conductive ring.

摘要翻译： 在一个实施例中，肖特基二极管结构包括通过肖特基接触开口与半导体材料接触的肖特基势垒层。 导电环形成在肖特基接触开口附近，并通过薄的绝缘层与半导体材料分离。 在该结构上形成另一绝缘层，并在其中形成接触开口。 接触开口比肖特基接触开口宽，露出导电环的一部分。 通过肖特基接触开口形成与半导体材料接触的肖特基势垒金属，并与导电环进一步形成+接触。

公开(公告)号：US20080111151A1

公开(公告)日：2008-05-15

申请号：US11791844

申请日：2005-12-01

申请人： Junichi Teraki ,  Mitsuhiro Tanaka

发明人： Junichi Teraki ,  Mitsuhiro Tanaka

IPC分类号： H01L31/111 ,  H01L21/00

CPC分类号： H01L25/072 ,  H01L23/3677 ,  H01L23/473 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/0272 ,  H05K1/0298 ,  H05K1/183 ,  H05K3/0061 ,  H05K7/20927 ,  H05K2201/064 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power module includes a power semiconductor, a non-power semiconductor, one resin substrate and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device is disposed in order to cool the power semiconductor.

摘要翻译： 功率模块包括功率半导体，非功率半导体，一个树脂基板和冷却装置。 功率半导体和非功率半导体构成用于进行电力转换的电源电路。 功率半导体和非功率半导体都安装在树脂基板上。 设置冷却装置以冷却功率半导体。

公开(公告)号：US07361957B2

公开(公告)日：2008-04-22

申请号：US11426037

申请日：2006-06-23

申请人： Kil Ho Kim ,  Yong Icc Jung

发明人： Kil Ho Kim ,  Yong Icc Jung

IPC分类号： H01L23/62 ,  H01L29/72 ,  H01L29/74 ,  H01L31/111 ,  H01L29/73

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed in predetermined regions on the semiconductor substrate, a gate formed in a predetermined region on the semiconductor substrate between the field oxide films, a well pick-up region formed in a predetermined region on the semiconductor substrate between the field oxide films, a source formed in a predetermined region on the semiconductor substrate between the field oxide film and the gate, a drain drift region formed in a predetermined region on the semiconductor substrate between the gate and the field oxide film, a drain active region of a concentration higher than that of the drain drift region, the drain active region being formed in the drain drift region, and an oxide film formed on the semiconductor substrate on a boundary of the drain drift region and the drain active region. Accordingly, the current concentrated on the surface of the device can be uniformly distributed over the entire device.

摘要翻译： 本发明涉及静电放电保护装置（ESD）。 根据本发明的实施例，一种用于静电放电保护的装置包括半导体衬底，形成在半导体衬底上的预定区域中的多个场氧化物膜，在半导体衬底上的预定区域之间形成的栅极氧化物 形成在半导体衬底上的场氧化物膜之间的预定区域中的阱拾取区域，形成在场氧化物膜和栅极之间的半导体衬底上的预定区域中的源极，形成在栅极氧化膜上的漏极漂移区域 在栅极和场氧化物膜之间的半导体衬底上的预定区域，具有比漏极漂移区域的浓度高的漏极有源区，在漏极漂移区中形成漏极有源区，以及形成在漏极漂移区上的氧化物膜 半导体衬底在漏极漂移区域和漏极活性区域的边界上。 因此，集中在装置表面上的电流可以均匀地分布在整个装置上。

公开(公告)号：US07332749B2

公开(公告)日：2008-02-19

申请号：US11073967

申请日：2005-03-07

申请人： Naohiro Shimizu ,  Takayuki Sekiya

发明人： Naohiro Shimizu ,  Takayuki Sekiya

IPC分类号： H01L29/32 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7392 ,  H03K3/57 ,  H03K17/567

摘要： A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thicknesses and impurity concentrations of a base region and a buffer region are determined such that a peak voltage obtained by a peak current at which a punch-through state is brought about does not exceed a breakdown voltage of the SIThy. Such design can achieve an SIThy having a self protecting function of autonomously preventing its breakdown without compromising a turn-on performance in which the peak voltage does not drastically exceed the breakdown voltage of the SIThy even when the peak current increases. Further, a compact SIThy capable of generating a short pulse can be achieved by reducing a gate-channel current-carrying area to a minimum.

摘要翻译： 提供了一种紧凑，便宜的静态感应晶闸管（SIThy），其在运行期间以较高的电压上升速率不太可能被分解并且用于能够产生高电压短脉冲的高压脉冲发生器 。 确定基极区域和缓冲区域的厚度和杂质浓度，使得通过引起穿通状态的峰值电流获得的峰值电压不超过SIThy的击穿电压。 这种设计可以实现具有自主防止其击穿的自我保护功能的SIThy，而不会影响即使峰值电流增加，峰值电压也不会大大超过SIThy的击穿电压的开启性能。 此外，可以通过将栅极通道载流区域最小化来实现能够产生短脉冲的紧凑的SIThy。

公开(公告)号：US20070262344A1

公开(公告)日：2007-11-15

申请号：US11208127

申请日：2005-08-18

申请人： A.F.M. Anwar ,  Richard T. Webster

发明人： A.F.M. Anwar ,  Richard T. Webster

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L29/49

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L27/12 ,  H01L29/0673 ,  H01L29/78696 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/938

摘要： An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire formed in the first trench operates to electrically couple the first and second electrodes. A second nanowire formed in the second trench operates to electrically couple the second and third electrodes. First drain and first source contacts may be respectively disposed on the first and second electrodes and a first gate contact may be disposed to be capacitively coupled to the first nanowire. Similarly, second drain and second source contacts may be respectively disposed on the second and third electrodes and a second gate contact may be disposed to be capacitively coupled to the second nanowire.

摘要翻译： 提供绝缘栅硅纳米线晶体管放大器结构，并且包括由电介质材料形成的衬底。 图案化的硅材料可以设置在衬底上，并且包括通过第一和第二沟槽在衬底上均匀间隔开的至少第一，第二和第三电极。 形成在第一沟槽中的第一纳米线用于电耦合第一和第二电极。 形成在第二沟槽中的第二纳米线用于电耦合第二和第三电极。 第一漏极和第一源极触点可以分别设置在第一和第二电极上，并且第一栅极接触可以被布置成电容耦合到第一纳米线。 类似地，第二漏极和第二源极触点可以分别设置在第二和第三电极上，并且第二栅极触点可以被布置成电容耦合到第二纳米线。

公开(公告)号：US07291869B2

公开(公告)日：2007-11-06

申请号：US11348221

申请日：2006-02-06

申请人： Ralf Otremba

发明人： Ralf Otremba

IPC分类号： H01L29/32 ,  H01L29/74 ,  H01L31/111 ,  H01L23/02 ,  H03K17/00

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An electronic module has a heat sink with an upper surface and a lower surface, a plurality of leads arranged adjacent the heat sink and at least one circuit element with two vertical semiconductor power switches. The two vertical semiconductor power switches of each circuit element are arranged in a stack and are configured to provide a half-bridge circuit having a node defining an output. The first vertical semiconductor power switch of each of the circuit elements is mounted on the upper surface of the heat sink by an electrically conductive layer such that the lower surface of the heat sink provides the ground contact area of the electronic module.

摘要翻译： 电子模块具有上表面和下表面的散热器，与散热片相邻布置的多个引线和具有两个垂直半导体功率开关的至少一个电路元件。 每个电路元件的两个垂直半导体功率开关被布置成堆叠并且被配置为提供具有定义输出的节点的半桥电路。 每个电路元件的第一垂直半导体功率开关通过导电层安装在散热器的上表面上，使得散热器的下表面提供电子模块的接地面积。

公开(公告)号：US20070254404A1

公开(公告)日：2007-11-01

申请号：US11380953

申请日：2006-05-01

申请人： Mark Gerber ,  Kurt Wachtler ,  Abram Castro

发明人： Mark Gerber ,  Kurt Wachtler ,  Abram Castro

IPC分类号： H01L31/111 ,  H01L23/02 ,  H01L21/00

CPC分类号： H05K1/141 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/162 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.

摘要翻译： 半导体系统（300）具有一个或多个封装的有源子系统（310,330）; 每个子系统具有基板，其具有电接触焊盘和堆叠在彼此之上的一个或多个半导体芯片，组装在基板上。 该系统还具有封装的无源子系统（320），其包括具有电触点的基板和无源电部件，例如电阻器，电容器和指示器。 被动子系统与有源子系统堆叠并通过焊料体与其连接。

公开(公告)号：US20070235753A1

公开(公告)日：2007-10-11

申请号：US11729577

申请日：2007-03-29

申请人： Maarten Debucquoy ,  Stijn Verlaak ,  Paul Heremans

发明人： Maarten Debucquoy ,  Stijn Verlaak ,  Paul Heremans

IPC分类号： H01L31/111 ,  H01L29/74 ,  H01L29/417

CPC分类号： H01L27/305 ,  B82Y10/00 ,  H01L27/307 ,  H01L51/0019 ,  H01L51/0036 ,  H01L51/0047 ,  H01L51/0053 ,  H01L51/0545 ,  H01L51/0562 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/428 ,  Y02E10/549

摘要： An organic photo-detecting field-effect device is presented, the device comprising a first layer comprising an organic semi-conducting material, the first layer acting as an accumulation layer and as a charge transport layer for a first type of charge carriers, and a second layer comprising a second material, the second layer acting as a an accumulation layer for a second type of charge carriers. Charges collected in the second layer influence the charge transport in the first layer. The second material may be an organic semi-conducting material or a metal. At the interface between the first layer and the second layer a heterojunction is formed in the case of an organic semi-conducting second material, and a Schottky barrier is formed in the case of a metal second material, giving rise to an efficient exciton splitting. Different geometries and operation modes facilitating the removal of the collected photo-generated charge carriers during the reset period of the device are presented. Furthermore, a method for operating an organic photo-detecting field-effect device is provided.

摘要翻译： 本发明提供了一种有机光电检测场效应器件，该器件包括第一层，该第一层包括有机半导体材料，第一层用作积聚层，以及用作第一类型电荷载流子的电荷传输层，以及 第二层包括第二材料，第二层用作第二类型电荷载体的累积层。 在第二层中收集的电荷影响第一层中的电荷传输。 第二材料可以是有机半导电材料或金属。 在第一层和第二层之间的界面处，在有机半导体第二材料的情况下形成异质结，并且在金属第二材料的情况下形成肖特基势垒，产生有效的激子分裂。 提出了在器件的复位周期期间有助于去除收集的光电载流子的不同几何形状和操作模式。 此外，提供了一种用于操作有机光电检测场效应器件的方法。

公开(公告)号：US07265041B2

公开(公告)日：2007-09-04

申请号：US11311995

申请日：2005-12-19

申请人： Schyi-yi Wu ,  Ji-hyoung Yoo

发明人： Schyi-yi Wu ,  Ji-hyoung Yoo

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L27/0207 ,  H01L29/4238

摘要： A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.

摘要翻译： 提供晶体管和制造晶体管的方法。 晶体管包括半导体材料，其包括以交替的行或列形成的漏极区域和源极区域。 晶体管还包括覆盖半导体材料的顶部的多晶硅链，其彼此断开并基本上彼此平行，并且将漏极区域与源极区域分开。 该方法包括提供半导体材料，在半导体材料的顶部上生长第一绝缘层，在第一绝缘层的顶部上沉积多晶硅层，在多晶硅层中限定多条链，多条链与 基本上彼此平行，并且以交替的行或列在半导体材料中形成多个漏极区域和多个源极区域。 多个链从多个源区域分离多个漏极区域。