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110 条记录 (耗时 0.032 秒)

    DELAY-LOCKED LOOP, DELAY LOCKING METHOD, CLOCK SYNCHRONIZATION CIRCUIT, AND MEMORY
    42.
    发明公开
    DELAY-LOCKED LOOP, DELAY LOCKING METHOD, CLOCK SYNCHRONIZATION CIRCUIT, AND MEMORY 审中-公开

    公开(公告)号：US20240056083A1

    公开(公告)日：2024-02-15

    申请号：US18450959

    申请日：2023-08-16

    申请人： Changxin Memory Technologies, Inc.

    发明人： Siman Li ,  YoonJoo Eom

    IPC分类号： H03K21/02 ,  H03K3/86 ,  H03K3/037

    CPC分类号： H03K21/02 ,  H03K3/86 ,  H03K3/037

    摘要： Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.

    INTEGRATED RING OSCILLATOR CLOCK GENERATOR
    44.
    发明申请
    INTEGRATED RING OSCILLATOR CLOCK GENERATOR 审中-公开

    公开(公告)号：US20180294801A1

    公开(公告)日：2018-10-11

    申请号：US15950762

    申请日：2018-04-11

    申请人： CHAOLOGIX, INC.

    发明人： Timothy Arthur BELL ,  Daniel F. YANNETTE

    IPC分类号： H03K3/03 ,  H03K3/011 ,  H03K3/86

    CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03K3/86

    摘要： A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.

    Semiconductor device, electronic component, and electronic device
    45.
    发明授权
    Semiconductor device, electronic component, and electronic device 有权
    半导体装置，电子部件和电子装置

    公开(公告)号：US09438207B2

    公开(公告)日：2016-09-06

    申请号：US14882816

    申请日：2015-10-14

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yoshiyuki Kurokawa

    IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K3/012 ,  H01L29/786 ,  H03K19/0944 ,  H03K3/86 ,  H03K3/356

    CPC分类号： H03K3/012 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/037 ,  H03K3/356 ,  H03K3/86 ,  H03K5/134 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/1776 ,  H03K2005/00195

    摘要： A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.

    摘要翻译： 半导体器件包括能够存储配置数据的逻辑电路。 逻辑电路包括锁存电路，运算电路，延迟电路和第一输出定时产生电路。 锁存电路具有接收脉冲信号和复位信号并输出​​第一信号的功能。 延迟电路具有接收第一信号并输出​​第二信号的功能。 第一个信号控制运算电路和延迟电路的电源。 通过延迟第一信号以便对应于算术电路的关键路径中的延迟来获得第二信号。 第一输出定时发生电路具有接收对第一信号和第二信号进行逻辑运算而获得的第三信号并输出​​复位信号的功能。

    Semiconductor device, semiconductor system and method for operating semiconductor device
    46.
    发明授权
    Semiconductor device, semiconductor system and method for operating semiconductor device 有权
    半导体器件，半导体系统和半导体器件的操作方法

    公开(公告)号：US09246496B2

    公开(公告)日：2016-01-26

    申请号：US14489157

    申请日：2014-09-17

    申请人： SK hynix Inc.

    发明人： Ji-Wan Jung

    IPC分类号： H03L7/081 ,  H03L7/08 ,  H03L7/083 ,  H03L7/10 ,  H03K3/86 ,  G06F1/08 ,  G06F1/32

    CPC分类号： H03L7/0802 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03K3/86 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/10

    摘要： A semiconductor device includes a code generation block configured to generate an output clock by delaying a reference clock which is inputted from an exterior, control a delay value of the output clock based on a result of comparing phases of the reference clock and a feedback clock, and generate a first control code corresponding to the delay value of the output clock, a voltage generation block configured to generate an internal voltage with a voltage level corresponding to the first control code, a clock generation block configured to generate an internal clock with a frequency corresponding to the first control code, and a feedback delay block configured to generate the feedback clock by delaying the output clock by a delay value corresponding to a second control code.

    摘要翻译： 一种半导体器件，包括代码生成块，其被配置为通过延迟从外部输入的参考时钟来生成输出时钟，基于比较参考时钟的相位和反馈时钟的结果来控制输出时钟的延迟值， 并产生与输出时钟的延迟值相对应的第一控制代码，电压产生块，被配置为产生具有与第一控制代码相对应的电压电平的内部电压;时钟产生模块，被配置为产生具有频率的内部时钟 以及反馈延迟块，被配置为通过将输出时钟延迟与第二控制码对应的延迟值来产生反馈时钟。

    Data processing circuit and solid-state imaging device
    47.
    发明授权
    Data processing circuit and solid-state imaging device 有权
    数据处理电路和固态成像装置

    公开(公告)号：US09160318B2

    公开(公告)日：2015-10-13

    申请号：US14030225

    申请日：2013-09-18

    申请人： OLYMPUS CORPORATION

    发明人： Yosuke Kusano

    IPC分类号： H03K3/86 ,  H01L27/146 ,  H04N5/378

    CPC分类号： H03K3/86 ,  H01L27/14601 ,  H04N5/378

    摘要： A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal.

    摘要翻译： 一种数据处理电路，其在输入锁存时钟的定时保持输入多相时钟的各相的时钟信号的状态，所述多相时钟包括以确定的一定间隔顺序移位的多个相的时钟信号 并且产生通过在输入锁存时钟的定时数字化多相时钟的相位状态而获得的数字信号，所述数据处理电路包括：锁存部分，包括n个锁存单元组（n是 每个锁存单元保持多相时钟的相应相位的时钟信号的状态，并输出指示该多相时钟的保持状态的输出信号， 时钟信号。

    SEMICONDUCTOR DEVICE
    49.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150042500A1

    公开(公告)日：2015-02-12

    申请号：US14336073

    申请日：2014-07-21

    申请人： Renesas Electronics Corporation

    发明人： Masaki FUJIWARA ,  Yasuo MORIMOTO ,  Takashi MATSUMOTO

    IPC分类号： H03K3/86 ,  H03M1/38

    CPC分类号： H03M1/125 ,  H03K5/133 ,  H03K2005/00065 ,  H03M1/12 ,  H03M1/38 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468

    摘要： To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

    摘要翻译： 提供能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号，该半导体器件检测当该周期从比较期间转变到该时间段时是否输出信号及其延迟信号 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。

    METHODS AND DEVICES RELATING TO TIME-VARIABLE SIGNAL PROCESSING
    50.
    发明申请
    METHODS AND DEVICES RELATING TO TIME-VARIABLE SIGNAL PROCESSING 有权
    与时变信号处理相关的方法和设备

    公开(公告)号：US20130300483A1

    公开(公告)日：2013-11-14

    申请号：US13890649

    申请日：2013-05-09

    申请人： The Royal Institution for the Advancement of Learning / McGill University

    发明人： Gordon Roberts ,  Mohammad Ali Bakhshian

    IPC分类号： H03K3/86

    CPC分类号： H03K3/86 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00052

    摘要： Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. Whilst driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.

    摘要翻译： 时间模式信号处理（TMSP）提供了一种在利用为数字应用设计的CMOS电路工艺时，抵消模拟电路设计中的一些挑战的手段。 因此，提供用于存储，加减时间模式变量的数字方法将是有益的，因为它们提供了提供TMSP技术并扩展其在设备，系统和应用中的利用的显着优点。 在CMOS工艺挑战的驱动下，概述的TM电路基本上可以利用任何数字电路技术，因为它们基于延迟。 本发明人提出了一种TM变量的方法，其中开关和采用开关延迟单元，使得两个上升信号边沿之间的瞬时相位差可被锁存并用于执行各种算术运算。 有利的是，该技术允许在数字电路内实现模拟采样数据信号处理。