公开(公告)号：US5981318A

公开(公告)日：1999-11-09

申请号：US993679

申请日：1997-12-18

Applicant: Richard A. Blanchard

Inventor： Richard A. Blanchard

IPC: H01L29/78 ,  H01L21/00 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66651 ,  H01L29/78603 ,  H01L29/78654

Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.

Abstract translation: 一种场效应晶体管结构，其中单个图案化薄膜半导体层是单晶体，并且在沟道位置中外延匹配并与基底体区域介电地隔离; 并且在源极/漏极位置处是多晶的，其邻接所述沟道位置。

公开(公告)号：US5977607A

公开(公告)日：1999-11-02

申请号：US447362

申请日：1995-05-23

Applicant: Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

Inventor： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

IPC: H01L21/32 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/32 ,  H01L21/76202

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

Abstract translation: 提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成衬垫氧化物层。 在衬垫氧化物层上形成第一氮化硅层。 然后在第一氮化硅层上形成多晶硅缓冲层。 在多晶硅层上形成第二氮化硅层。 在第二氮化硅层上形成并图案化光致抗蚀剂层。 通过第二氮化硅层和多晶硅缓冲层蚀刻开口以暴露第一氮化硅层的一部分。 至少在开口中暴露的多晶硅缓冲层上形成第三氮化硅区域。 在开口中蚀刻第一氮化硅层。 然后在开口中形成场氧化物区域。

公开(公告)号：US5963025A

公开(公告)日：1999-10-05

申请号：US994738

申请日：1997-12-19

Applicant: Gianluca Colli

Inventor： Gianluca Colli

IPC: G05F3/24 ,  G05F3/26 ,  H02M3/07 ,  G05F1/575

CPC classification number: H02M3/073 ,  G05F3/242 ,  G05F3/267

Abstract: A voltage regulator (400) having a charge pump includes a bias current circuit (402) which produces a bias current (I.sub.bias). The bias current (I.sub.bias) is mirrored by a first mirror circuit (404) and multiplied by gain stage Q4.sub.beta and mirrored again by a factor "c" on the output of DMOS2. The same I.sub.bias is mirrored by a ratio "b" and multiplied by the product of Q5.sub.beta and Q6.sub.beta. The push-pull current operation at the output terminal (416) is obtained by turning on and off switches SW1 (418) and SW2 (420) that are controlled by a clock signal. The voltage regulator (400) further includes an output voltage clamp (424) that keeps control of the V.sub.boost voltage by controlling the amount of bias current (I.sub.bias).

Abstract translation: 具有电荷泵的电压调节器（400）包括产生偏置电流（Ibias）的偏置电流电路（402）。 偏置电流（Ibias）被第一镜像电路（404）镜像，并与增益级Q4beta相乘，并在DMOS2的输出上再次被因子“c”镜像。 相同的Ibias由比例“b”反映，并乘以Q5beta和Q6beta的乘积。 通过接通和断开由时钟信号控制的开关SW1（418）和SW2（420）来获得输出端子（416）处的推挽电流操作。 电压调节器（400）还包括通过控制偏置电流量（Ibias）来保持对Vboost电压的控制的输出电压钳位（424）。

公开(公告)号：US5951690A

公开(公告)日：1999-09-14

申请号：US762608

申请日：1996-12-09

Applicant: Yehuda Baron ,  Jefferson E. Owen ,  Darryn D. McDade

Inventor： Yehuda Baron ,  Jefferson E. Owen ,  Darryn D. McDade

IPC: G11B20/00 ,  G11B20/10 ,  G11B27/10 ,  G11B27/30 ,  H04N5/85 ,  H04N9/804 ,  H04N21/2368 ,  H04N21/434 ,  G06F1/12

CPC classification number: H04N9/8042 ,  G11B20/00007 ,  G11B20/10527 ,  G11B27/10 ,  G11B27/3027 ,  H04N21/4143 ,  H04N21/42646 ,  H04N21/4305 ,  H04N21/4307 ,  G11B2220/2562 ,  H04N5/85

Abstract: A DVD player that integrates a DVD device into a personal computer is provided. As such, the personal computer is able to output audio-visual works from a DVD CD-ROM. When integrating a DVD device with a personal computer, various problems must be overcome. For example, in a personal computer, the video display is controlled by a graphics controller, and in order to render an audio-visual stream in a personal computer, the audio-visual stream and the graphics controller must be synchronized. The synchronization problem arises because the graphics controller only displays data at the beginning of 33.4 millisecond time intervals. Thus, although the audio portion may be played almost immediately, the video portion may have to wait for up to 33.4 milliseconds before being displayed. In this manner, the audio portion and the video portion become unsynchronized which means that the audio portion plays before the corresponding video portion is displayed. The DVD player solves this problem by synchronizing the start of the audio-visual stream with the graphics controller so that the time at which a video sequence is displayed coincides with one of the graphics controller's 33.4 millisecond time intervals.

Abstract translation: 提供将DVD设备集成到个人计算机中的DVD播放器。 因此，个人计算机能够从DVD CD-ROM输出视听作品。 当将DVD设备与个人计算机集成时，必须克服各种问题。 例如，在个人计算机中，视频显示由图形控制器控制，并且为了在个人计算机中呈现视听流，视听流和图形控制器必须同步。 出现同步问题是因为图形控制器仅在33.4毫秒的时间间隔开始显示数据。 因此，虽然可以立即播放音频部分，但是在显示之前视频部分可能必须等待多达33.4毫秒。 以这种方式，音频部分和视频部分变得不同步，这意味着音频部分在相应的视频部分被显示之前播放。 DVD播放机通过将视听流的开始与图形控制器同步来解决这个问题，使得显示视频序列的时间与图形控制器的33.4毫秒时间间隔一致。

公开(公告)号：US5945738A

公开(公告)日：1999-08-31

申请号：US760098

申请日：1996-12-03

Applicant: Loi N. Nguyen ,  Frank R. Bryant ,  Artur P. Balasinski

Inventor： Loi N. Nguyen ,  Frank R. Bryant ,  Artur P. Balasinski

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L24/05 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0248 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/14

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract translation: 提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。 通过第一介电层形成第一开口以暴露扩散区域的一部分。 在第一开口中以及与第一开口相邻的第一电介质层的一部分上形成双重多晶硅着陆焊盘。 双层焊盘优选由两个多晶硅着陆焊盘形成，其中氧化物形成在两个多晶硅层的一部分之间并在第一多晶硅层上方。 该着陆垫将在制造的这个阶段增强晶片的平面化，并且容许随后形成的金属触点的未对准而不会侵入设计规则。

公开(公告)号：US5939909A

公开(公告)日：1999-08-17

申请号：US52187

申请日：1998-03-31

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03K4/00 ,  H03K4/94 ,  H03K17/16 ,  H03B1/00

CPC classification number: H03K17/166 ,  H03K17/163 ,  H03K4/00 ,  H03K4/94

Abstract: A driver circuit for a power device of a power driving stage is capable of providing slew rate control. The driver circuit includes the following elements: a charging source of current, a discharging source of current, a first switch, a second switch, a conductive device, a capacitive element, an amplifier, and the power device. Both the first and second switches receive a control signal. The elements of the driver circuit are configured such that the conductive device will conduct only when the following two conditions are met: the control signal is a certain logic level and the voltage generated by the amplifier is larger than a reference voltage. When the control signal transitions from a first to a second logic state, a charging current is delivered to the capacitive element, an output voltage of the driver circuit increased to the reference voltage, and a voltage on a control terminal of the power device also increases to a charge pump voltage level. When the control signal transitions from the second to the first logic state, the conductive device conducts as long as the output voltage generated by the power device is larger than the reference voltage and the discharging source of current operates to quickly discharge the capacitive element so that the voltage at the node at the input terminal of the amplifier is quickly reduced until it approximates the reference voltage.

Abstract translation: 用于动力驱动级的动力装置的驱动电路能够提供压摆率控制。 驱动器电路包括以下元件：电流充电源，电流放电源，第一开关，第二开关，导电器件，电容元件，放大器和功率器件。 第一和第二开关都接收控制信号。 驱动器电路的元件被配置为仅当满足以下两个条件时导通器件才会导通：控制信号是一定的逻辑电平，放大器产生的电压大于参考电压。 当控制信号从第一逻辑状态转变到第二逻辑状态时，将充电电流传送到电容元件，驱动电路的输出电压增加到参考电压，并且功率器件的控制端上的电压也增加 到电荷泵电压电平。 当控制信号从第二逻辑状态转变到第一逻辑状态时，只要由功率器件产生的输出电压大于参考电压并且电流放电源工作以使电容元件快速放电，导电器件就会导通，使得 放大器输入端节点处的电压迅速降低，直到其接近参考电压。

公开(公告)号：US5927992A

公开(公告)日：1999-07-27

申请号：US251781

申请日：1994-05-31

Applicant: Robert L. Hodges ,  Frank R. Bryant

Inventor： Robert L. Hodges ,  Frank R. Bryant

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/3145 ,  H01L21/32 ,  H01L21/76202 ,  H01L21/76216 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/954

Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation. The composite dielectric layer is then patterned and etched to form the dielectric portion of various integrated circuit devices.

Abstract translation: 提供一种用于形成半导体集成电路的改进的器件电介质的方法，以及根据该集成电路形成的集成电路。 对于用于亚微米体系的缩放几何形状，在与场氧化物区域相邻的多个有效区域上形成用作器件电介质的复合介电层。 在形成场氧化物区域之前形成复合电介质层，并且包括无孔氮化硅层。 无孔氮化硅层优选包括覆盖衬底的薄氮化区的薄沉积氮化硅层。 在随后在多个有效区域之间形成场氧化物区域期间，氮化硅层被部分氧化。 在形成场氧化物区域之前，可以在氮化硅层上方形成氧化物层，然后在场氧化物形成期间将其致密化。 然后对复合介电层进行构图和蚀刻，以形成各种集成电路器件的电介质部分。

公开(公告)号：US5894158A

公开(公告)日：1999-04-13

申请号：US769185

申请日：1991-09-30

Applicant: Che-Chia Wei

Inventor： Che-Chia Wei

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/66492 ,  H01L21/823814 ,  H01L29/6659

Abstract: A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

Abstract translation: 掩模用于集成电路器件中的轻掺杂漏极和光晕注入。 掩模只露出与场效应晶体管栅电极相邻的衬底的部分。 由于光晕植入仅在晶体管通道附近进行，在其中它执行有用的功能，因此获得了足够的器件可靠性和性能。 由于从不需要的有源区的那些部分掩盖光晕注入，所以有源区域结电容降低。 这种降低的电容导致提高的晶体管切换速度。 用于限定轻掺杂的漏极和晕圈注入区域的掩模可以容易地由已经存在的栅极和有源区域几何形状的直接组合形成。

公开(公告)号：US5889515A

公开(公告)日：1999-03-30

申请号：US762616

申请日：1996-12-09

Applicant: Darryn D. McDade ,  Jefferson E. Owen

Inventor： Darryn D. McDade ,  Jefferson E. Owen

IPC: G06F1/12 ,  G06F1/08 ,  G06T1/00 ,  G11B20/00 ,  G11B27/10 ,  G11B27/30 ,  H04N5/04 ,  H04N5/765 ,  H04N5/92 ,  H04N7/26 ,  G06F17/00

CPC classification number: G11B20/00007 ,  G06F1/08 ,  G11B27/105 ,  G11B27/3027 ,  H04N5/765

Abstract: A DVD CD-ROM player integrated with a personal computer is provided. When integrating a DVD CD-ROM with a personal computer, there are various problems that must be overcome. For example, the stream from the DVD CD-ROM utilizes a 27 MHz clock. However, a personal computer typically does not have a 27 MHz clock, but instead has a system clock, that runs at the frequency of the processor. Therefore, in order to play a DVD-based audio-visual work in a personal computer, a clock running at 27 MHz is needed. As such, a software clock running at 27 MHz is provided which facilitates the integration of a DVD CD-ROM into a personal computer. By using a software clock, synchronization of the audio-visual stream is facilitated and both cost and development time are reduced.

Abstract translation: 提供与个人计算机集成的DVD CD-ROM播放器。 当将DVD光盘与个人计算机集成时，存在必须克服的各种问题。 例如，来自DVD CD-ROM的流使用27MHz时钟。 然而，个人计算机通常不具有27MHz时钟，而是具有以处理器的频率运行的系统时钟。 因此，为了在个人计算机中播放基于DVD的视听工作，需要以27MHz运行的时钟。 因此，提供了以27MHz运行的软件时钟，其有助于将DVD CD-ROM集成到个人计算机中。 通过使用软件时钟，便于视听流的同步，降低成本和开发时间。

公开(公告)号：US5883479A

公开(公告)日：1999-03-16

申请号：US886324

申请日：1997-07-01

Applicant: Paolo Menegoli ,  Gianluca Colli

Inventor： Paolo Menegoli ,  Gianluca Colli

IPC: G05F3/26 ,  G11B19/20 ,  H02H7/08 ,  H02P6/00 ,  H02P6/24

CPC classification number: H02P6/00 ,  G11B19/20 ,  H02H7/0833

Abstract: A circuit and method to clamp a node of a power device connected to a driving node of a polyphase d-c motor to a reference potential during a powering off of the drive includes a current mirror and a comparator. A first input of the comparator is connected to the reference potential, and a second input is connected to the driving node. The reference potential may be a ground potential, or, preferably, the potential at another driving node of the motor. An output of the comparator is connected to a first side of the current mirror. A circuit is connected to apply a current reflecting the output of the comparator to a low side driver connected to the node.

Abstract translation: 在驱动器断电期间将连接到多相d-c电动机的驱动节点的功率器件的节点钳位到参考电位的电路和方法包括电流镜和比较器。 比较器的第一输入端连接到参考电位，第二输入端连接到驱动节点。 参考电位可以是接地电位，或者优选地，电动机的另一个驱动节点处的电位。 比较器的输出端连接到电流镜的第一侧。 连接电路以将反映比较器的输出的电流施加到连接到节点的低侧驱动器。