公开(公告)号：US20160190303A1

公开(公告)日：2016-06-30

申请号：US14588116

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Hong HE ,  Bruce DORIS

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract translation: 制造结构稳定的绝缘体上的FinFET的方法使用氮化硅衬垫来防止在SiGe鳍的基底处的去稳定化氧化。 氮化硅衬垫阻止氧气进入翅片的下角，以便制造高浓度SiGe翅片。 氮化硅衬垫即使其厚度小于约5nm也是有效的。 使用SiN衬垫为具有较高锗含量，在25-55％锗浓度范围内的翅片提供结构稳定性。

公开(公告)号：US20160190031A1

公开(公告)日：2016-06-30

申请号：US14582581

申请日：2014-12-24

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Godfrey Dimayuga

IPC: H01L23/36

CPC classification number: H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: One or more embodiments are directed to semiconductor packages with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.

Abstract translation: 一个或多个实施例涉及具有一个或多个悬臂垫的半导体封装。 在一个实施例中，凹部位于面向悬臂垫的封装的衬底中。 悬臂焊盘包括形成有导电球的导电焊盘。 悬臂垫被配置成吸收作用在包装上的应力。

公开(公告)号：US20160187484A1

公开(公告)日：2016-06-30

申请号：US14587130

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John Bloomfield ,  Kenneth Weiner

IPC: G01S17/32 ,  H01S5/30 ,  H01S5/183 ,  G01S17/88 ,  H01L31/107

CPC classification number: G01S17/32 ,  B65H23/1825 ,  B65H23/1955 ,  B65H26/08 ,  B65H2403/942 ,  B65H2511/142 ,  B65H2553/412 ,  B65H2557/512 ,  G01S17/08 ,  G01S17/88 ,  H01L31/107 ,  H01S5/183 ,  H01S5/3013 ,  B65H2220/03

Abstract: A sensing device is for sensing an outer surface of a roll of material. An infrared (IR) laser source is configured to direct IR laser radiation to the outer surface of the roll of material. A single photon avalanche diode (SPAD) detector is configured to receive reflected IR laser radiation from the outer surface of the roll of material. A controller is coupled to the IR laser source and the SPAD detector to determine a distance to the outer surface of the roll of material based upon a time-of-flight of the IR laser radiation.

Abstract translation: 感测装置用于感测材料卷的外表面。 红外（IR）激光源被配置为将IR激光辐射引导到材料卷的外表面。 单光子雪崩二极管（SPAD）检测器被配置为从材料卷的外表面接收反射的IR激光辐射。 基于IR激光辐射的飞行时间，控制器耦合到IR激光源和SPAD检测器以确定到材料卷的外表面的距离。

公开(公告)号：US20160185283A1

公开(公告)日：2016-06-30

申请号：US14585374

申请日：2014-12-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Kenneth WEINER ,  John BLOOMFIELD

IPC: B60Q1/44 ,  B60Q1/26 ,  B60T7/04

CPC classification number: B60Q1/444 ,  B60Q1/44 ,  B60Q1/441

Abstract: A braking intensity indicator system for a vehicle of a type that includes a foot operated brake pedal and at least one brake light may include a proximity sensor to be associated with the brake pedal and a controller. The controller may be configured to cooperate with the proximity sensor to determine a plurality of brake pedal positions versus time during foot operation of the brake pedal, and selectively adjust an intensity of the at least one brake light based upon the determined plurality of brake pedal positions versus time.

Abstract translation: 一种用于车辆的制动强度指示器系统，其包括脚踏操纵的制动踏板和至少一个制动灯，可包括与制动踏板相关联的接近传感器和控制器。 控制器可以被配置为与接近传感器协作以在制动踏板的脚踏操作期间确定多个制动踏板位置与时间的关系，并且基于所确定的多个制动踏板位置来选择性地调节至少一个制动灯的强度 相对于时间。

公开(公告)号：US20160183369A1

公开(公告)日：2016-06-23

申请号：US14579902

申请日：2014-12-22

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Frederick Ray Gomez

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/4842 ,  H01L21/4825 ,  H01L21/54 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/10628 ,  H05K2201/10992 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.

Abstract translation: 本公开的实施例涉及具有形成在引线的外表面中的凹部的引线框封装。 这些凹部填充有诸如焊料的填充材料。 凹槽中的填充材料提供用于填充材料（例如焊料）的可润湿表面，以在将包装安装到诸如印刷电路板（PCB）的另一装置时粘附。 这使得封装引线与PCB之间能够实现强焊点。 它还可以在安装包装后改善焊点的目视检查。

公开(公告)号：US20160181390A1

公开(公告)日：2016-06-23

申请号：US14581857

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Chun-chen YEH ,  Ruilong XIE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L29/51 ,  H01L21/311 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/45 ,  H01L21/76816 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/5386 ,  H01L29/401 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.

Abstract translation: 本公开涉及一种用于降低晶体管中线的电阻的装置和方法。 晶体管具有形成在栅极，漏极和源极上方并电连接的电触点。 连接到栅极的电触点包括沉积在栅极上的钨接触构件和沉积在钨接触构件上的铜触点。 连接到漏极和源极的电触头包括沉积在漏极和源极区域上的钨部分，以及沉积在钨部分上的铜触点。

公开(公告)号：US20160181381A1

公开(公告)日：2016-06-23

申请号：US14577431

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

Abstract translation: FinFET器件包括半导体鳍片，在鳍片的沟道上延伸的栅极电极和在栅电极的每一侧上的侧壁间隔物。 电介质材料位于所述散热片的底部的每一侧上，其中在散热片的每侧的氧化物材料覆盖在电介质材料上。 在通道区域的每一侧的翅片上形成的凹陷区域由氧化物材料界定。 凸起的源极区域填充凹陷区域并且在栅电极的第一侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。 凸起的漏极区域填充凹陷区域并且在栅电极的第二侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。

公开(公告)号：US20160172497A1

公开(公告)日：2016-06-16

申请号：US14975534

申请日：2015-12-18

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US09368411B2

公开(公告)日：2016-06-14

申请号：US14596625

申请日：2015-01-14

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made on the bottom portion to produce a silicon-germanium region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 硅 - 锗半导体材料的外延生长在底部制成以产生硅 - 锗区。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US20160163850A1

公开(公告)日：2016-06-09

申请号：US14560255

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7848

Abstract: A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

Abstract translation: FinFET晶体管包括具有在沟道区域上延伸的晶体管栅电极的半导体材料的鳍。 从晶体管栅电极的两侧的鳍延伸的第一外延生长材料的引出源区和漏区。 源极和漏极接触开口延伸穿过预金属化电介质材料以到达升高的源极和漏极区域。 第二外延生长材料的源极和漏极接触区域在源极和漏极接触开口的底部处从第一外延生长材料延伸。 金属材料填充源极和漏极接触开口，以分别与源极和漏极接触区域形成源极和漏极接触。 漏极接触区域可以从晶体管栅电极偏移足以在第一外延生长材料的升高的源极区域内提供横向扩散的金属氧化物半导体（LDMOS）配置的偏移距离。