公开(公告)号：US20170141913A1

公开(公告)日：2017-05-18

申请号：US15138573

申请日：2016-04-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Benoit Durand ,  Massimo Cervetto ,  Christophe Laurencin

IPC: H04L9/00 ,  G06F21/85 ,  G06F21/74

CPC classification number: H04L9/004 ,  G06F21/556 ,  G06F21/74 ,  G06F21/85 ,  G06F2221/2123 ,  G06F2221/2127

Abstract: A circuit includes a first processing unit and a second identical processing unit. A first communication bus passes encrypted data between one of a plurality of functions and one or both of the first and second processing units. A selection circuit determines whether the encrypted bus is coupled to the first processing unit, the second processing unit, or both of the first and second processing units.

公开(公告)号：US20170117326A1

公开(公告)日：2017-04-27

申请号：US15398228

申请日：2017-01-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L29/732

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

公开(公告)号：US20170084336A1

公开(公告)日：2017-03-23

申请号：US15365367

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

公开(公告)号：US20170063523A1

公开(公告)日：2017-03-02

申请号：US15046069

申请日：2016-02-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Bruneau

IPC: H04L9/00 ,  H04L9/06

CPC classification number: G09C1/00 ,  H04L9/003 ,  H04L9/0631 ,  H04L2209/043 ,  H04L2209/046

Abstract: A method of protecting a Rijndael-type algorithm executed by an electronic circuit against side channel attacks, wherein: each block of data to be encrypted or to be decrypted is masked with a first mask before a non-linear block substitution operation is applied based on a substitution box, and is then unmasked with a second mask after the substitution; and the substitution box is recalculated, block by block, before the non-linear operation is applied, the processing order of the blocks of the substitution box being submitted to a random permutation, commutative with the non-linear substitution operation.

Abstract translation: 一种保护由电子电路执行的针对侧信道攻击的Rijndael型算法的方法，其中：在应用非线性块替换操作之前，将要被加密或要解密的每个数据块以第一掩码进行掩码 替换框，然后在替换后用第二个掩码进行掩码; 并且在应用非线性操作之前逐个重新计算替换盒，替换盒的块的处理顺序被提交到随机排列，与非线性替换操作交换。

公开(公告)号：US20170048658A1

公开(公告)日：2017-02-16

申请号：US15335636

申请日：2016-10-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  STMICROELECTRONICS GMBH

Inventor： PIERRE RIZZO ,  ALEXANDRE CHARLES ,  JUERGEN BOEHLER ,  THIERRY MEZIACHE

IPC: H04W4/00

CPC classification number: H04W4/80 ,  G06K7/0008 ,  G06K7/10237 ,  G06K7/10247 ,  H04B5/0031

Abstract: Device, comprising a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract translation: 一种装置，包括主元件（ME）和一组至少两个辅助元件（SEi），所述主元件包括主SWP接口（MINT），每个辅助元件包括连接到所述主SWP的从SWP接口（SLINTi） 所述NFC元件的接口通过可控地切换的SWP链路（LK）和被配置为控制所述SWP链路切换的管理装置（PRM，CTLM，AMGi），以便在所述SWP链路上一次仅选择性地激活一个从属SWP接口。

公开(公告)号：US09563787B2

公开(公告)日：2017-02-07

申请号：US15060159

申请日：2016-03-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yannick Teglia

IPC: G06F7/04 ,  G06F17/30 ,  H04N7/16 ,  G06F21/62 ,  G06F21/56 ,  G06F21/79 ,  G06F12/14

CPC classification number: G06F21/6218 ,  G06F12/1425 ,  G06F12/1483 ,  G06F21/561 ,  G06F21/566 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/034

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.

Abstract translation: 一种用于保护针对病毒的易失性存储器的方法，其中：写入，读取或执行的权限被分配给存储器的某些区域; 并且作为该区域的内容的授权或禁止的操作码的第一列表与这些区域中的每一个相关联。

公开(公告)号：US20170012671A1

公开(公告)日：2017-01-12

申请号：US15042326

申请日：2016-02-12

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Pierre DEMAJ ,  Yoann Bouvet

IPC: H04B3/54

CPC classification number: H04B3/544 ,  H04B3/466 ,  H04B3/542 ,  H04B2203/5495 ,  H04L5/006 ,  H04L25/023 ,  H04L27/2649

Abstract: A method is for processing a channel analog signal coming from a transmission channel. The method may include converting the channel analog signal into a channel digital signal, and detecting a state of the transmission channel based on the channel digital signal to detect whether the transmission channel is, over an interval of time, one or more of linear and time invariant and linear and cyclostationary.

公开(公告)号：US20170012666A1

公开(公告)日：2017-01-12

申请号：US15042509

申请日：2016-02-12

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Pierre Demaj ,  Yoann Bouvet

IPC: H04B3/54 ,  H04L27/26 ,  H04L5/00

CPC classification number: H04B3/54 ,  H04L5/0007 ,  H04L5/0044 ,  H04L27/2601 ,  H04L27/2647

Abstract: A method is for processing an analog channel signal from a transmission channel. The analog channel signal conveys frames, the transmission channel being linear and cyclostationary for a duration of a frame. The method may include converting of the analog channel signal into a digital channel signal, and performing channel estimations for the frame based upon the digital channel signal to generate a sequence of N transfer functions of the transmission channel. Each of the sequence of N transfer functions may be respectively associated with N successive time slices. The method may include decoding at least some symbols of the frame using, for each of the symbols, a transfer function associated with a successive time slice including a respective symbol.

Abstract translation: 一种用于处理来自传输信道的模拟信道信号的方法。 模拟信道信号传送帧，传输信道在帧的持续时间内是线性的和循环平稳的。 该方法可以包括将模拟信道信号转换为数字信道信号，以及基于数字信道信号对帧执行信道估计，以产生传输信道的N个传递函数的序列。 N个传送函数的每个序列可以分别与N个连续时间片相关联。 该方法可以包括使用针对每个符号的与包括相应符号的连续时间片相关联的传递函数来对帧的至少一些符号进行解码。

公开(公告)号：US09543311B2

公开(公告)日：2017-01-10

申请号：US14625356

申请日：2015-02-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C16/14 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/266 ,  H01L21/3213

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract translation: 各种实施例提供了一种存储单元，其包括垂直选择栅极，在衬底上方延伸的浮置栅极，其中浮置栅极还在非零重叠距离上延伸在垂直选择栅极的一部分上方，存储器单元包括掺杂 注入在与选择栅极相对延伸的垂直沟道区域和与浮动栅极相对延伸的水平沟道区域的交点处的区域。

公开(公告)号：US20160372561A1

公开(公告)日：2016-12-22

申请号：US15252090

申请日：2016-08-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L29/423 ,  H01L27/115 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

Abstract translation: 形成在半导体衬底中的存储单元包括在衬底中形成的沟槽中垂直延伸的选择栅极，并且通过栅极氧化物的第一层与衬底隔离，水平浮动栅极延伸在衬底上方并与衬底隔离，并与衬底隔离 栅极氧化物的第二层和在浮置栅极上方延伸的水平控制栅极。 选择栅极覆盖浮动栅极的侧面。 浮置栅极仅由第一层栅极氧化物与选择栅极分离，并且与垂直沟道区分离，仅沿着选择栅极在衬底中延伸，仅由栅极氧化物的第二层分离。