公开(公告)号：US09997431B2

公开(公告)日：2018-06-12

申请号：US15451862

申请日：2017-03-07

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Rafael Augusto Prieto Herrera ,  Jean-Philippe Colonna ,  Perceval Coudrain

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L23/433

CPC classification number: H01L23/3672 ,  H01L23/3185 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2224/81

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

公开(公告)号：US09991173B2

公开(公告)日：2018-06-05

申请号：US14155891

申请日：2014-01-15

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H01L21/8249 ,  H01L29/747 ,  H01L27/02 ,  H01L29/87 ,  H01L29/06

CPC classification number: H01L21/8249 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/747 ,  H01L29/87

Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate, thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.

公开(公告)号：US20180096844A1

公开(公告)日：2018-04-05

申请号：US15594763

申请日：2017-05-15

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Victorien Paredes-Saez

IPC: H01L21/02 ,  C30B25/10 ,  C30B25/14 ,  C30B25/02

CPC classification number: H01L21/02381 ,  C30B25/02 ,  C30B25/10 ,  C30B25/14 ,  C30B25/183 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02496 ,  H01L21/02532 ,  H01L21/0262

Abstract: A gas phase epitaxial deposition method deposits silicon, germanium, or silicon-germanium on a single-crystal semiconductor surface of a substrate. The substrate is placed in an epitaxy reactor swept by a carrier gas. The substrate temperature is controlled to increase to a first temperature value. Then, for a first time period, at least a first silicon precursor gas and/or a germanium precursor gas introduced. Then, the substrate temperature is decreased to a second temperature value. At the end of the first time period and during the temperature decrease, introduction of the first silicon precursor gas and/or the introduction of a second silicon precursor gas is maintained. The gases preferably have a partial pressure adapted to the formation of a silicon layer having a thickness smaller than 0.5 nm.

公开(公告)号：US09929039B2

公开(公告)日：2018-03-27

申请号：US15129328

申请日：2015-03-27

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre ,  Herve Jaouen

IPC: H01L29/04 ,  H01L21/763 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/763 ,  H01L29/04

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

公开(公告)号：US20180083602A1

公开(公告)日：2018-03-22

申请号：US15460520

申请日：2017-03-16

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Pascal Urard

IPC: H03K3/356 ,  H03K3/012 ,  H03K19/00

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/35625 ,  H03K19/0002

Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.

公开(公告)号：US20180039320A1

公开(公告)日：2018-02-08

申请号：US15467614

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Silvia Brini ,  Chittoor Parthasarathy

IPC: G06F1/32 ,  G06F11/32 ,  G06F15/78 ,  G06F11/30

CPC classification number: G06F1/3262 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3024 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/327 ,  G06F15/7814 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.

公开(公告)号：US09870947B1

公开(公告)日：2018-01-16

申请号：US15632878

申请日：2017-06-26

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Didier Campos ,  Benoit Besancon ,  Perceval Coudrain ,  Jean-Philippe Colonna

IPC: H01L23/29 ,  H01L21/78 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00 ,  H01L21/782 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/782 ,  H01L23/29 ,  H01L23/36 ,  H01L23/373 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

公开(公告)号：US20180012965A1

公开(公告)日：2018-01-11

申请号：US15427656

申请日：2017-02-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/36 ,  H01L29/786

CPC classification number: H01L29/36 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78648

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

公开(公告)号：US09859319B2

公开(公告)日：2018-01-02

申请号：US14923799

申请日：2015-10-27

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Axel Crocherie ,  Jean-Pierre Oddou ,  Stéphane Allegret-Maret ,  Hugues Leininger

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14607 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.

公开(公告)号：US09838572B2

公开(公告)日：2017-12-05

申请号：US14848962

申请日：2015-09-09

Applicant: STMICROELECTRONICS SA

Inventor： Manu Alibay ,  Stéphane Auberger

IPC: H04N5/14 ,  H04N5/232 ,  G06T7/246 ,  G06T7/277

CPC classification number: H04N5/145 ,  G06T7/246 ,  G06T7/277 ,  G06T2207/10016 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23277

Abstract: The method includes for each current pair of first and second successive video images determining movement between the two images. The determining includes a phase of testing homography model hypotheses on the movement by a RANSAC type algorithm operating on a set of points in the first image and first assumed corresponding points in the second image so as to deliver one of the homography model hypothesis that defines the movement. The test phase includes a test of first homography model hypotheses of the movement obtained from a set of second points in the first image and second assumed corresponding points in the second image. At least one second homography model hypothesis is obtained from auxiliary information supplied by an inertial sensor and representative of a movement of the image sensor between the captures of the two successive images of the pair.