Self-calibrating polymer nano composite (PNC) sensing element

    公开(公告)号:US11656193B2

    公开(公告)日:2023-05-23

    申请号:US17346049

    申请日:2021-06-11

    IPC分类号: G01N27/20

    CPC分类号: G01N27/20

    摘要: Aspects of the present application allow for measurement of a calibrated resistance for a resistive film in a sensing element, such that effects from contact resistance and background resistance drifts due to factors such as temperature, strain or aging can be reduced or eliminated. In some embodiments, by taking a plurality of two-terminal resistance measurements between various pairs of electrodes on a resistive film, a contact-resistance-independent resistance of a reference portion of the resistive film can be determined. Further, a contact-resistance-independent resistance of a sensing portion of the resistive film can be determined based on a plurality of two-terminal resistance measurements between pairs of electrodes. The resistance of the reference portion can be removed from the measured resistance of the sensing portion, such that variations in the reference portion resistance that are not caused by a sensed environmental condition may be compensated.

    Current sensing techniques for power converter circuits

    公开(公告)号:US11652415B2

    公开(公告)日:2023-05-16

    申请号:US17325000

    申请日:2021-05-19

    IPC分类号: H02M3/158 H02M1/00

    摘要: A current sensing technique for coupled inductors in switching regulator circuits, where the current sensing technique can provide the current information needed for a power converter design and can be implemented as a real-world solution. The current sensing techniques can provide complete information of the coupled inductor current, such as peak current, valley current, and intermediate ripples. The current sensing techniques can use a simple RC network, such as two resistors and two capacitors for 2-phase operation. The techniques, however, are not limited to two-phase operation. The current sensing techniques of this disclosure can be extended to power stage assembly implementations, e.g., DrMOS modules, with current output in order to increase signal-to-noise ratio, which is significant for reliable control. In addition, the current sensing techniques of this disclosure can be extended to multi-phase operation, such as three or more phases.

    Apparatus and methods for high-speed drivers

    公开(公告)号:US11640367B1

    公开(公告)日:2023-05-02

    申请号:US17450585

    申请日:2021-10-12

    发明人: Wei-Hung Chen

    IPC分类号: G06F13/42

    摘要: Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.

    ANALOG-TO-DIGITAL CONVERSION CIRCUIT WITH IMPROVED LINEARITY

    公开(公告)号:US20230117529A1

    公开(公告)日:2023-04-20

    申请号:US18066053

    申请日:2022-12-14

    IPC分类号: H03M1/46 H03M1/12

    摘要: Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

    Multi quantizer loops for delta-sigma converters

    公开(公告)号:US11621722B2

    公开(公告)日:2023-04-04

    申请号:US17459020

    申请日:2021-08-27

    IPC分类号: H03M3/00

    摘要: The number of bits in the quantizer can be decoupled from the number of bits in the feedback digital-to-analog converter (DAC) A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and a second quantizer coupled to an output of the first quantizer, where the second quantizer can receive the output of the first quantizer and generate an output having a second number of bits. The feedback DAC can be coupled to the second quantizer to receive a representation of the output of the second quantizer, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.