公开(公告)号：US07177260B2

公开(公告)日：2007-02-13

申请号：US10141774

申请日：2002-05-10

Applicant: Dae-sik Kim ,  Kun-ho Cho ,  Soon-kyo Hong ,  Young-il Kim ,  Kwang-sup Im ,  Ho-cheol Lee ,  Dae-hwan Kim

Inventor： Dae-sik Kim ,  Kun-ho Cho ,  Soon-kyo Hong ,  Young-il Kim ,  Kwang-sup Im ,  Ho-cheol Lee ,  Dae-hwan Kim

IPC: G11B7/135 ,  G02B5/04

CPC classification number: G11B7/1359 ,  G02B5/04 ,  G11B2007/0006

Abstract: An optical pickup including a many-sided reflection prism formed as a single body with a plurality of reflection faces to guide a light beam incident through a transmission face in a horizontal direction perpendicular to a height direction by reducing a size of the light beam in the height direction, by using a difference in angles between the reflection faces, and to reflect the guided light beam in the height direction by one reflection face of an angle less than 45° with respect to the horizontal direction. By using the many-sided reflection prism, the height of an optical system can be reduced regardless of the wavelength used without reducing light beam size. Thereby, slim-sized optical pickups can be implemented.

Abstract translation: 一种光学拾取器，其包括多个反射棱镜，其形成为具有多个反射面的单体，以通过减小在高度方向上的光束的尺寸来引导在垂直于高度方向的水平方向上通过透射面入射的光束 通过使用反射面之间的角度差，并且将导向光束在高度方向上反射相对于水平方向的角度小于45°的一个反射面。 通过使用多面反射棱镜，可以减小光学系统的高度，而不管使用的波长而不减小光束尺寸。 因此，可以实现细长尺寸的光学拾取器。

公开(公告)号：US06928023B2

公开(公告)日：2005-08-09

申请号：US10465553

申请日：2003-06-20

Applicant: Ho-Cheol Lee ,  Jung-Soo Ryoo

Inventor： Ho-Cheol Lee ,  Jung-Soo Ryoo

IPC: G11C7/00 ,  G11C5/06 ,  G11C5/14 ,  G11C8/12

CPC classification number: G11C5/063 ,  G11C5/14 ,  G11C8/12

Abstract: A method of controlling a bank voltage (AIVC) through memory block selection information, said method comprising the steps of detecting an array block selection signal of an array block disposed distantly from an AIVC driver in response to an activated memory array block selection signal; and supplying a second bank voltage to a memory bank by driving a normal size driver and an oversize driver when detecting the array block selection signal for the distantly disposed array block.

Abstract translation: 一种通过存储块选择信息控制存储体电压（AIVC）的方法，所述方法包括以下步骤：响应激活的存储器阵列块选择信号，检测远离AIVC驱动器的阵列块的阵列块选择信号; 以及当检测到用于远处布置的阵列块的阵列块选择信号时，通过驱动正常尺寸的驱动器和超大驱动器，将第二存储体电压提供给存储体。

公开(公告)号：US06337829B1

公开(公告)日：2002-01-08

申请号：US09648283

申请日：2000-08-24

Applicant: Ho Cheol Lee

Inventor： Ho Cheol Lee

IPC: G11C800

CPC classification number: G11C29/88 ,  G11C29/883

Abstract: A semiconductor memory device which includes a plurality of memory cell array blocks, each block including 2n partial blocks selectable in response to n address bits among a plurality of bits address. A partial block select signal generator is used for selecting ½n partial blocks of the 2n partial blocks in each of the plurality of memory cell array blocks by selecting the state of corresponding address bits among the n address bits. A method for repairing a semiconductor memory device which includes a plurality of memory cell array blocks and 2n partial blocks selected by the plurality of memory cell array blocks each responding to n address bits among a plurality of address bits, the method includes selecting only the ½n functional partial blocks of the 2n partial blocks in each of the plurality of memory cell array blocks by selecting the state of corresponding address bits among the n bits of address information.

Abstract translation: 一种半导体存储器件，包括多个存储单元阵列块，每个块包括响应于多个位地址中的n个地址位而可选择的2n个部分块。 通过选择n个地址位中相应的地址位的状态，使用部分块选择信号发生器来选择多个存储单元阵列块中的每一个中的2n个部分块的1/2个部分块。 一种修复半导体存储器件的方法，该半导体存储器件包括多个存储单元阵列块和由多个存储单元阵列块选择的2n个部分块，每个部分块响应多个地址位中的n个地址位，该方法包括仅选择½n 通过选择地址信息的n位中的相应地址位的状态，在多个存储单元阵列块的每一个中的2n个部分块的功能部分块。

公开(公告)号：US06259642B1

公开(公告)日：2001-07-10

申请号：US09553514

申请日：2000-04-20

Applicant: Sang-joon Hwang ,  Ho-cheol Lee

Inventor： Sang-joon Hwang ,  Ho-cheol Lee

IPC: G11C702

CPC classification number: G11C7/18 ,  G11C8/08 ,  G11C8/12

Abstract: A semiconductor memory device having reduced sensing noise and sensing current by reducing the number of cells activated by a word line is provided. The semiconductor memory device includes a memory cell array, which is segmented into a plurality of memory cell groups in a column direction, and a plurality of sub-word line drivers for selectively activating the sub-word line of a corresponding memory cell group in response to a group selection signal. The semiconductor memory device prevents sensing operation from occurring in a memory cell group which is not selected, while sensing operation is performed in a memory cell group which is selected by the group selection signal.

Abstract translation: 提供了通过减少由字线激活的单元的数量而具有降低的感测噪声和感测电流的半导体存储器件。 半导体存储器件包括在列方向上被分割为多个存储单元组的存储单元阵列和用于响应地选择性地激活对应的存储单元组的子字线的多个子字线驱动器 到组选择信号。 半导体存储器件防止在由组选择信号选择的存储单元组中执行感测操作时在未选择的存储单元组中发生感测操作。

公开(公告)号：US5631871A

公开(公告)日：1997-05-20

申请号：US578151

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  B01F7/00 ,  B01F13/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5598371A

公开(公告)日：1997-01-28

申请号：US565292

申请日：1995-11-30

Applicant: Ho-Cheol Lee ,  Seung-Hun Lee

Inventor： Ho-Cheol Lee ,  Seung-Hun Lee

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  G11C13/00 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1078

Abstract: A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.

Abstract translation: 一种包括多个存储单元的半导体存储器件的数据输入/输出感测电路，该电路包括：存储单元的输入/输出线; 连接到存储单元外部的数据输入/输出端子; 连接在输入/输出线路和数据输入/输出端子之间的单个数据输入/输出线路; 感测单元，用于检测数据输入/输出线中是否提供有效数据，从而产生感测信号; 输出驱动单元，用于响应于感测信号将数据输入/输出线的数据发送到数据输入/输出端; 以及写入驱动单元，用于响应于感测信号输入数据输入/输出端子的数据。

公开(公告)号：US5191484A

公开(公告)日：1993-03-02

申请号：US828120

申请日：1992-01-30

Applicant: Jye-Sye Yeon ,  Jong-Jin Lee ,  Ho-Cheol Lee

Inventor： Jye-Sye Yeon ,  Jong-Jin Lee ,  Ho-Cheol Lee

IPC: G11B7/09

CPC classification number: G11B7/0935

Abstract: An optical pick-up objective lens driving apparatus comprises a rectangular moving member mounted for movement relative to an iron-core member in rectilinear focusing and tracking directions, respectively. The moving member carries focusing and tracking coils, and a lens. Magnetic pieces are disposed at respective corners of the moving member in opposing spacial relationship to magnetic plates of the iron core member to create a restoring force which biases the moving member to a pre-set position. The lens is mounted over a center of weight of the moving member.

Abstract translation: 光学拾取物镜驱动装置包括分别安装成相对于铁芯件在直线聚焦和跟踪方向上移动的矩形移动部件。 移动构件携带聚焦跟踪线圈和透镜。 磁片以与铁芯构件的磁性板相对的空间关系设置在移动构件的各个角上，以产生将移动构件偏压到预定位置的恢复力。 透镜安装在移动部件的重心上。

公开(公告)号：US08278992B2

公开(公告)日：2012-10-02

申请号：US12845279

申请日：2010-07-28

Applicant: So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

Inventor： So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

IPC: G05F1/10

CPC classification number: G11C5/14

Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.

Abstract translation: 一种在半导体器件中执行的内部电压产生方法，所述内部电压产生方法包括产生对应于多个外部电源电压的多个初始化信号; 检测来自所述多个初始化信号中的最后生成的初始化信号的转变并产生检测信号; 以及根据检测信号产生第一内部电压。

公开(公告)号：US20120163413A1

公开(公告)日：2012-06-28

申请号：US13177103

申请日：2011-07-06

Applicant: Jung-sik Kim ,  Dong-hyuk Lee ,  Ho-cheol Lee ,  Jang-woo Ryu

Inventor： Jung-sik Kim ,  Dong-hyuk Lee ,  Ho-cheol Lee ,  Jang-woo Ryu

IPC: H01L35/02 ,  G01K13/00

CPC classification number: H01L23/5258 ,  G01K7/01 ,  G01K13/10 ,  H01L23/34 ,  H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01068

Abstract: A semiconductor device, memory device, system, and method of using a stacked structure for stably transmitting signals among a plurality of semiconductor layers is disclosed. The device includes at least a first semiconductor chip including a first temperature sensor circuit configured to output first temperature information related to the first semiconductor chip, and at least one through substrate via.

Abstract translation: 公开了一种半导体器件，存储器件，系统以及使用层叠结构在多个半导体层之间稳定地传输信号的方法。 该装置至少包括第一半导体芯片，该第一半导体芯片包括第一温度传感器电路，该第一温度传感器电路被配置为输出与第一半导体芯片相关的第一温度信息，以及至少一个穿过基板通孔。

公开(公告)号：US08122199B2

公开(公告)日：2012-02-21

申请号：US12392432

申请日：2009-02-25

Applicant: Jin-Hyoung Kwon ,  Kyung-Woo Nam ,  Han-Gu Sohn ,  Ho-Cheol Lee ,  Kwang-Myeong Jang

Inventor： Jin-Hyoung Kwon ,  Kyung-Woo Nam ,  Han-Gu Sohn ,  Ho-Cheol Lee ,  Kwang-Myeong Jang

IPC: G06F12/00

CPC classification number: G11C11/413 ,  G11C7/1075

Abstract: A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

Abstract translation: 多端口半导体存储器件包括： 分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域 端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一 和第二个处理器通过共享内存区域。