Method of preparation for imide-substituted polymer
    52.
    发明申请
    Method of preparation for imide-substituted polymer 审中-公开
    酰亚胺取代聚合物的制备方法

    公开(公告)号:US20070093638A1

    公开(公告)日:2007-04-26

    申请号:US10559142

    申请日:2004-05-13

    CPC classification number: C08F8/32 C08F8/48 C08F222/08 C08F212/08

    Abstract: The present invention provides a method for manufacturing the imide-substituted polymer comprising the following four consecutive steps of (i) the copolymerization step of copolymerizing aromatic vinyl monomers and unsaturated dicarboxylic anhydride monomers, (ii) the separation step of removing the unreacted monomers and solvents from the abovementioned copolymerized solution continuously supplied to the separator, (iii) the imide substitution step of reacting unsaturated dicarboxylic anhydride units in said copolymers with primary amines, and (iv) the devolatilization step of removing low-molecular-weight volatiles from the polymer solution. The imide-substituted polymer manufactured according to the methods in the present invention has greatly improved the heat resistance and the productivity as the content of aromatic vinyl homopolymers is reduced significantly and the reaction time is shortened extensively.

    Abstract translation: 本发明提供一种制备酰亚胺取代聚合物的方法,包括以下四个连续步骤:(i)共聚芳族乙烯基单体和不饱和二羧酸酐单体的共聚步骤,(ii)除去未反应的单体和溶剂的分离步骤 从上述连续供给到分离器的共聚溶液中,(iii)将所述共聚物中的不饱和二羧酸酐单元与伯胺反应的酰亚胺取代步骤,和(iv)从聚合物溶液中除去低分子量挥发物的脱挥发分步骤 。 根据本发明的方法制备的酰亚胺取代的聚合物随着芳族乙烯基均聚物的含量显着降低并且反应时间被广泛地缩短而大大提高了耐热性和生产率。

    BODY BIASING STRUCTURE OF SOI
    55.
    发明申请
    BODY BIASING STRUCTURE OF SOI 有权
    SOI的身体偏心结构

    公开(公告)号:US20060278927A1

    公开(公告)日:2006-12-14

    申请号:US11423696

    申请日:2006-06-12

    CPC classification number: H01L29/78615

    Abstract: A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect on an SOI substrate can be prevented.

    Abstract translation: 提供了在SOI衬底上串联连接的器件的体偏置结构。 根据一些实施例,公共源极/漏极区的浅结使得所有器件只能像SOI传统体MOSFET在SOI衬底上仅偏移一个体接触,并且可以防止在SOI衬底上的浮体效应。

    View port of a chemical vapor deposition device for manufacturing semiconductor devices
    58.
    发明授权
    View port of a chemical vapor deposition device for manufacturing semiconductor devices 有权
    用于制造半导体器件的化学气相沉积装置的视图

    公开(公告)号:US06367415B2

    公开(公告)日:2002-04-09

    申请号:US09800894

    申请日:2001-03-08

    CPC classification number: B01J3/004 C23C16/488 G02B7/007

    Abstract: A view port of chemical vapor deposition apparatus for manufacturing semiconductor devices prevents heat loss in a chamber during a plasma deposition process. The view port includes a bracket protruding at the circumference of an opening in an electrode serving as a wall of a chamber of the apparatus, a transparent window pressed by the bracket against the wall via an O-ring, a pivoting cap for capping an opening in the bracket aligned with the window, and heat-insulative material and/or a heating element integral with the cap so as to be positioned close to the window when the cap is closed. The heating element can be a resistive heating wire or a warm air duct formed by a hose or the like. During the deposition process, the temperature of the window is maintained, thereby minimizing the tendency of polymer to adhere to the window.

    Abstract translation: 用于制造半导体器件的化学气相沉积设备的观察口防止在等离子体沉积过程中室内的热损失。 所述视口包括在所述设备的室的壁的开口的圆周处突出的支架,由所述托架通过O形环压靠在所述壁上的透明窗,用于封盖开口的枢转盖 在与窗口对齐的支架中,以及绝热材料和/或与盖一体的加热元件,以便当盖关闭时定位成靠近窗口。 加热元件可以是电阻加热线或由软管等形成的暖风管道。 在沉积过程中,保持窗口的温度,从而最小化聚合物粘附到窗口的趋势。

    Power semiconductor device having low on-resistance and high breakdown voltage
    59.
    发明授权
    Power semiconductor device having low on-resistance and high breakdown voltage 有权
    具有低导通电阻和高击穿电压的功率半导体器件

    公开(公告)号:US06344676B1

    公开(公告)日:2002-02-05

    申请号:US09533824

    申请日:2000-03-24

    Abstract: A power semiconductor device having low on-resistance and a high breakdown voltage is disclosed. The power semiconductor device can be a high power MOS transistor or an insulation gate bipolar transistor. The power semiconductor device has unit cells formed in parallel body region strips. A highly-doped drift layer of the same conductivity type as that of a drift region is provided between adjacent body region strips in a unit cell. Both ends of each of the body region strips of the unit cell are connected to a single frame region. This prevents a depletion region of a spherical or cylindrical type from being formed on an edge of the body region, and in so doing, increases a breakdown voltage of the device.

    Abstract translation: 公开了具有低导通电阻和高击穿电压的功率半导体器件。 功率半导体器件可以是高功率MOS晶体管或绝缘栅双极晶体管。 功率半导体器件具有以平行体区带形成的单元电池。 在单元电池中的相邻体区带之间设置与漂移区相同导电类型的高掺杂漂移层。 单元电池的每个体区带的两端连接到单个框架区域。 这防止了在体区域的边缘上形成球形或圆柱形的耗尽区,并且这样做增加了器件的击穿电压。

    Optical waveguide and method for fabricating the same
    60.
    发明授权
    Optical waveguide and method for fabricating the same 失效
    光波导及其制造方法

    公开(公告)号:US06339667B1

    公开(公告)日:2002-01-15

    申请号:US09484060

    申请日:2000-01-18

    CPC classification number: G02B6/13 G02B6/105 G02B6/132

    Abstract: Disclosed is an optical waveguide having a specific dopant distribution capable of reducing a deformation thereof and existence of residual stresses therein, thereby involving no birefrigence. A method for fabricating the optical waveguide is also disclosed. The optical waveguide includes a substrate, a lower clad layer doped with a dopant in a content varying continuously in a thickness direction of the lower clad layer, so that the lower clad layer exhibits a refractive index distribution varying in the thickness direction thereof, and a core layer formed over the lower clad layer.

    Abstract translation: 公开了具有能够减小其变形和在其中残留应力的存在的特定掺杂剂分布的光波导,从而不涉及双折射。 还公开了一种用于制造光波导的方法。 光波导包括衬底,掺杂有在下包层的厚度方向上连续变化的掺杂剂的下包层,使得下包层具有在其厚度方向上变化的折射率分布,并且 芯层形成在下包层上。

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