公开(公告)号：US06245753B1

公开(公告)日：2001-06-12

申请号：US09300173

申请日：1999-04-27

Applicant: Youngro Byun ,  Yong-Kyu Lee

Inventor： Youngro Byun ,  Yong-Kyu Lee

IPC: A61K31727

CPC classification number: C08B37/0075 ,  A61K31/727 ,  A61K47/542 ,  A61K47/554 ,  C08B37/00 ,  Y10S977/773 ,  Y10S977/775 ,  Y10S977/905 ,  Y10S977/915

Abstract: Polysaccharides, which are widely used as an anticoagulation drugs, especially heparin, are clinically administered only by intravenous or subcutaneous injection because of their strong hydrophilicity and high negative charge. Amphiphilic heparin derivatives were synthesized by conjugate to bile acids, sterols, and alkanoic acids, respectively. The hydrophobicity of the heparin derivatives depended on the feed mole ratio of heparin to hydrophobic agent. The heparin derivatives were slightly hydrophobic and exhibited good solubility in a water-acetone solvent, as well as water. The heparin derivatives have a high anticoagulant activity. These slightly hydrophobic heparin derivatives can be absorbed in gastric intestinal tract and can be used as oral dosage form. Also, the heparin derivatives can be used for the surface modification to prevent anticoagulation for medical devices such as extracorporeal devices and implanted devices.

Abstract translation: 广泛用作抗凝药物，特别是肝素的多糖由于其亲水性强，负电荷高，临床上仅通过静脉内或皮下注射给药。 两亲肝素衍生物分别通过与胆汁酸，甾醇和链烷酸共轭合成。 肝素衍生物的疏水性取决于肝素与疏水剂的进料摩尔比。 肝素衍生物略微疏水，在水 - 丙酮溶剂以及水中表现出良好的溶解性。 肝素衍生物具有高抗凝活性。 这些轻微疏水的肝素衍生物可以在胃肠道中被吸收并且可以作为口服剂型使用。 此外，肝素衍生物可用于表面改性以防止诸如体外器件和植入装置之类的医疗装置的抗凝。

公开(公告)号：US20170345475A1

公开(公告)日：2017-11-30

申请号：US15402231

申请日：2017-01-09

Applicant: Choong-Jae LEE ,  Gwan-Hyeob KOH ,  Bo-Young SEO ,  Yong-Kyu LEE

Inventor： Choong-Jae LEE ,  Gwan-Hyeob KOH ,  Bo-Young SEO ,  Yong-Kyu LEE

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/22 ,  G11C13/0002

Abstract: A resistive-type memory device is disclosed. The resistive-type memory device includes a memory cell array and a control logic circuit. The control logic circuit accesses the memory cell array in response to a command and an address provided from an outside. The memory cell array includes at least a first group of resistive-type memory cells and a second group of resistive-type memory cells. Each of the first group of resistive-type memory cells has a first feature size and each of the second group of resistive-type memory cells has a second feature size that is different from the first feature size.

公开(公告)号：US09583534B2

公开(公告)日：2017-02-28

申请号：US14795882

申请日：2015-07-09

Applicant: Choong-jae Lee ,  Hong-kook Min ,  Bo-young Seo ,  Aliaksei Ivaniukovich ,  Yong-kyu Lee

Inventor： Choong-jae Lee ,  Hong-kook Min ,  Bo-young Seo ,  Aliaksei Ivaniukovich ,  Yong-kyu Lee

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/228 ,  H01L29/1045 ,  H01L29/7833 ,  H01L29/7835 ,  H01L43/08

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract translation: 半导体器件包括能够以低功率执行多个功能的磁阻器件。 半导体器件包括单元晶体管，其中第一杂质区域和第二杂质区域分别布置在沟道方向上的沟道区域的两侧，连接到单元晶体管的第一杂质区域的源极线和磁体 电阻器件连接到单元晶体管的第二杂质区域。 相对于形状和杂质浓度分布中的至少一种，第一杂质区域和第二杂质区域围绕单元晶体管的沟道方向的中心不对称。

公开(公告)号：US20160126289A1

公开(公告)日：2016-05-05

申请号：US14795882

申请日：2015-07-09

Applicant: Choong-jae LEE ,  Hong-kook MIN ,  Bo-young SEO ,  Aliaksei IVANIUKOVICH ,  Yong-kyu LEE

Inventor： Choong-jae LEE ,  Hong-kook MIN ,  Bo-young SEO ,  Aliaksei IVANIUKOVICH ,  Yong-kyu LEE

IPC: H01L27/22 ,  H01L29/08 ,  H01L29/78 ,  H01L43/02

CPC classification number: H01L27/228 ,  H01L29/1045 ,  H01L29/7833 ,  H01L29/7835 ,  H01L43/08

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract translation: 半导体器件包括能够以低功率执行多个功能的磁阻器件。 半导体器件包括单元晶体管，其中第一杂质区域和第二杂质区域分别布置在沟道方向上的沟道区域的两侧，连接到单元晶体管的第一杂质区域的源极线和磁体 电阻器件连接到单元晶体管的第二杂质区域。 相对于形状和杂质浓度分布中的至少一种，第一杂质区域和第二杂质区域围绕单元晶体管的沟道方向的中心不对称。

公开(公告)号：US09142294B2

公开(公告)日：2015-09-22

申请号：US13797089

申请日：2013-03-12

Applicant: Yong-Kyu Lee ,  Bo-Geun Kim

Inventor： Yong-Kyu Lee ,  Bo-Geun Kim

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72

Abstract: A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.

Abstract translation: 一种用于电阻性非易失性存储器件的写入方法包括当数据为第一数据类型时，使用上/下写入脉冲信号将数据写入电阻性非易失性存储单元，并且仅使用上写入中的一种将数据写入电阻性非易失性存储单元 当数据是第二数据类型时，脉冲信号和下降写入脉冲信号。

公开(公告)号：US20140204650A1

公开(公告)日：2014-07-24

申请号：US13797089

申请日：2013-03-12

Applicant: YONG-KYU LEE ,  BO-GEUN KIM

Inventor： YONG-KYU LEE ,  BO-GEUN KIM

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72

Abstract: A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.

Abstract translation: 一种用于电阻性非易失性存储器件的写入方法包括当数据为第一数据类型时，使用上/下写入脉冲信号将数据写入电阻性非易失性存储单元，并且仅使用上写入中的一种将数据写入电阻性非易失性存储单元 当数据是第二数据类型时，脉冲信号和下降写入脉冲信号。

公开(公告)号：US20120018797A1

公开(公告)日：2012-01-26

申请号：US13168257

申请日：2011-06-24

Applicant: Tea-Kwang YU ,  Yong-Tae KIM ,  Byung-Sup SHIM ,  Yong-Kyu LEE ,  Bo-Young SEO ,  Ji-Hoon PARK

Inventor： Tea-Kwang YU ,  Yong-Tae KIM ,  Byung-Sup SHIM ,  Yong-Kyu LEE ,  Bo-Young SEO ,  Ji-Hoon PARK

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76895 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region.

Abstract translation: 非易失性存储器件包括限定半导体衬底中的有源区的器件隔离膜，形成在有源区的上部并具有第一导电类型的凹穴阱区，形成在有源区上并延伸到相交的栅电极 有源区，隧道绝缘膜，电荷存储膜和顺序地设置在有源区和栅电极之间的阻挡绝缘膜，分别形成在有源区和栅极的第一区和第二区中的源区和漏区 在所述栅电极的两侧露出，并且具有与所述第一导电类型相反的第二导电类型的凹穴结区，形成在与所述源极区相邻的所述第一区域中并且与所述凹穴阱区接触并且具有第一 导电型，以及形成在第一区域中的金属硅化物层，并且与源极区域和凹穴阱结区域接触。

公开(公告)号：US07777256B2

公开(公告)日：2010-08-17

申请号：US12132148

申请日：2008-06-03

Applicant: Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

Inventor： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

IPC: H01L21/8238

CPC classification number: H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

Abstract translation: 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子栅极结构和衬底内的离子阱结结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

公开(公告)号：US20100167487A1

公开(公告)日：2010-07-01

申请号：US12723265

申请日：2010-03-12

Applicant: Myung-Jo Chun ,  Hee-Seong Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

Inventor： Myung-Jo Chun ,  Hee-Seong Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

IPC: H01L21/336

CPC classification number: H01L27/11293 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665

Abstract: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

Abstract translation: 掩模只读存储器（MROM）器件分别包括形成在衬底的单元和离子区域的第一和第二栅电极。 第一杂质区形成在基板的单电池区域上，以便与第一栅电极相邻。 形成与第一杂质区相同导电类型的第二杂质区，以与第二栅电极的侧壁间隔开。 第四杂质区形成在离电池区域，从第二杂质区延伸并与第二栅电极的侧壁重叠。 第四杂质区域具有与第二杂质区域相反的导电类型，并且深度大于第二杂质区域的深度。

公开(公告)号：US07733696B2

公开(公告)日：2010-06-08

申请号：US11818238

申请日：2007-06-13

Applicant: Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

Inventor： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

IPC: G11C11/34

CPC classification number: G11C16/0433 ,  G11C8/10 ,  G11C16/08 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

Abstract: A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

Abstract translation: 非易失性集成电路存储器件可以包括具有相同导电类型的第一和第二电隔离阱的半导体衬底。 可以在第一阱上提供第一多个非易失性存储单元晶体管，并且可以在第二阱上提供第二多个非易失性存储单元晶体管。 本地控制栅极线可以与第一和第二多个非易失性存储单元晶体管电耦合，并且组选择晶体管可以电耦合在本地控制栅极线和全局控制栅极线之间。 更具体地，组选择晶体管可以被配置为响应于施加到组选择晶体管的栅极的组选择栅极信号来电耦合和去耦合本地控制栅极线和全局控制栅极线。 还讨论了相关方法和系统。