Estimating flash quality using selective error emphasis
    51.
    发明授权
    Estimating flash quality using selective error emphasis 有权
    使用选择性错误强调估算闪光质量

    公开(公告)号:US09594615B2

    公开(公告)日:2017-03-14

    申请号:US14501081

    申请日:2014-09-30

    Applicant: APPLE INC.

    Abstract: A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.

    Abstract translation: 一种用于数据存储的方法包括:从存储器件读取作为相应模拟值存储在一组存储器单元中的数据,并将读出的数据中的读出错误分类为至少第一和第二不同类型,这取决于模拟 价值下降。 基于第一和第二类型的读出错误的评估数,将强调第二类型的读出错误的存储器质量分配给存储器单元组。

    GLDPC SOFT DECODING WITH HARD DECISION INPUTS
    52.
    发明申请
    GLDPC SOFT DECODING WITH HARD DECISION INPUTS 审中-公开
    具有硬决策输入的GLDPC软解码

    公开(公告)号:US20160182087A1

    公开(公告)日:2016-06-23

    申请号:US14574411

    申请日:2014-12-18

    Applicant: APPLE INC.

    Abstract: A decoder includes circuitry and a soft decoder. The circuitry is configured to receive channel hard decisions for respective bits of a Generalized Low-Density Parity Check (GLDPC) code word that includes multiple component code words, including first and second component code words having one or more shared bits, to schedule decoding of the GLDPC code word, and following the decoding, to output the decoded GLDPC code word. The soft decoder is configured to receive the channel hard decisions corresponding to the first component code word, to further receive soft reliability measures that were assigned to the shared bits in decoding the second component code word, and to decode the first component code word based on the channel hard decisions and the soft reliability measures.

    Abstract translation: 解码器包括电路和软解码器。 电路被配置为接收包括多个分量码字的广义低密度奇偶校验(GLDPC)码字的各个比特的信道硬判决,该多个分量码字包括具有一个或多个共享比特的第一和第二分量码字,以调度 GLDPC码字,并在解码之后,输出解码的GLDPC码字。 软解码器被配置为接收与第一分量码字相对应的信道硬判决,以进一步接收在解码第二分量码字时分配给共享比特的软可靠性度量,并且基于 渠道硬决策和软可靠性措施。

    Statistical peak-current management in non-volatile memory devices
    53.
    发明授权
    Statistical peak-current management in non-volatile memory devices 有权
    非易失性存储器件的统计峰值电流管理

    公开(公告)号:US09361951B2

    公开(公告)日:2016-06-07

    申请号:US14468661

    申请日:2014-08-26

    Applicant: Apple Inc.

    Abstract: A method includes, in a storage system that includes multiple memory devices, holding a definition of a given type of storage command. Multiple storage commands of the given type are executed in the memory devices, such that an actual current consumption of each storage command deviates from a nominal current waveform defined for the given type by no more than a predefined deviation, and such that each storage command is preceded by a random delay.

    Abstract translation: 一种方法包括在包括多个存储设备的存储系统中,保持给定类型的存储命令的定义。 给定类型的多个存储命令在存储器件中被执行,使得每个存储命令的实际电流消耗偏离为给定类型定义的额定电流波形不超过预定义的偏差,并且使得每个存储命令是 之前是随机延迟。

    Management of Data Storage in Memory Cells Using a Non-Integer Number of Bits Per Cell
    55.
    发明申请
    Management of Data Storage in Memory Cells Using a Non-Integer Number of Bits Per Cell 审中-公开
    使用非整数每个单元的位数来管理存储单元中的数据存储

    公开(公告)号:US20160012883A1

    公开(公告)日:2016-01-14

    申请号:US14858313

    申请日:2015-09-18

    Applicant: Apple Inc.

    Abstract: A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

    Abstract translation: 一种用于数据存储的方法包括:通过使用至少一个外部代码和一个内部代码对数据进行编码,以及在将编码数据存储在存储器单元中之前可选地反转编码数据,将数据存储在一组存储单元中。 从存储器单元读取编码数据,并将内码解码应用于读取的编码数据以产生解码结果。 根据内部代码的解码结果,至少部分读取数据有条件地反转。

    Error correction coding over multiple memory pages
    57.
    发明授权
    Error correction coding over multiple memory pages 有权
    通过多个内存页进行纠错编码

    公开(公告)号:US09136879B2

    公开(公告)日:2015-09-15

    申请号:US13921446

    申请日:2013-06-19

    Applicant: Apple Inc.

    CPC classification number: H03M13/29 G06F11/1012 G11C29/00 G11C2029/1804

    Abstract: A method for data storage includes encoding each of multiple data items individually using a first Error Correction Code (ECC) to produce respective encoded data items. The encoded data items are stored in a memory. The multiple data items are encoded jointly using a second ECC, so as to produce a code word of the second ECC, and only a part of the code word is stored in the memory. The stored encoded data items are recalled from the memory and the first ECC is decoded in order to reconstruct the data items. Upon a failure to reconstruct a given data item from a respective given encoded data item by decoding the first ECC, the given data item is reconstructed based on the part of the code word of the second ECC and on the encoded data items other than the given encoded data item.

    Abstract translation: 一种用于数据存储的方法包括使用第一纠错码(ECC)分别对多个数据项中的每一个进行编码,以产生相应的编码数据项。 编码数据项存储在存储器中。 多个数据项使用第二ECC共同编码,以便产生第二ECC的代码字,并且仅一部分代码字被存储在存储器中。 存储的编码数据项被从存储器调用,并且第一ECC被解码以便重构数据项。 在通过解码第一ECC无法从相应的给定编码数据项重构给定数据项时,基于第二ECC的代码字的部分和除了给定的编码数据项之外的编码数据项重建给定数据项 编码数据项。

    High-performance ECC decoder
    58.
    发明授权
    High-performance ECC decoder 有权
    高性能ECC解码器

    公开(公告)号:US09136871B2

    公开(公告)日:2015-09-15

    申请号:US14182802

    申请日:2014-02-18

    Applicant: Apple Inc.

    Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

    Abstract translation: 用于纠错码(ECC)解码的方法包括从表示已经用ECC编码的数据的一组位产生综合征。 错误定位器多项式(ELP)是基于综合征产生的。 识别至少一些ELP根,并校正由这些根指示的错误。 可以通过应用向量空间中的比特向量操作来产生每个综合征。 通过使用向量空间的不同基础应用向量运算来产生每个综合征。 可以通过使用串行乘法器对ELP系数进行操作,在给定的场元件上评估ELP,其中每个串行乘法器执行乘法循环序列,并在每个周期中产生中间结果。 响应于检测至少一个中期结果,指示给定的元素不是ELP根,在完成序列之前终止乘法循环。

    Memory device with internal signal processing unit
    59.
    发明授权
    Memory device with internal signal processing unit 有权
    内存信号处理单元

    公开(公告)号:US09086993B2

    公开(公告)日:2015-07-21

    申请号:US14306764

    申请日:2014-06-17

    Applicant: Apple Inc.

    Abstract: A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

    Abstract translation: 一种用于操作存储器的方法包括:通过将输入存储值写入到一组模拟存储器单元中,将数据存储在制造在第一半导体管芯上的多个模拟存储器单元中。 在存储数据之后,使用相应的不同的阈值集合读取组中每个模拟存储器单元的多个输出存储值,从而提供分别对应于阈值集合的输出存储值的多个输出组。 输出存储值的多个输出组由在第一半导体管芯上制造的电路预处理,以产生预处理的数据。 预处理数据被提供给存储器控制器,该存储器控制器制造在与第一半导体管芯不同的第二半导体管芯上。 以使得存储器控制器能够响应于预处理的数据重构数据。

    SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS
    60.
    发明申请
    SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS 审中-公开
    模拟记忆体阵列中编程方案的选择性激活

    公开(公告)号:US20150055388A1

    公开(公告)日:2015-02-26

    申请号:US14526833

    申请日:2014-10-29

    Applicant: Apple Inc.

    CPC classification number: G11C27/005 G11C7/02 G11C11/5628 G11C16/3418

    Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

    Abstract translation: 一种用于数据存储的方法包括:定义第一编程方案,其编程一组模拟存储器单元,同时减少由与该组相邻的至少一个存储器单元引起的干扰;以及第二编程方案,其对该组模拟存储器单元进行编程 不能减少第一编程方案减少的所有干扰。 基于针对模拟存储器单元定义的标准来选择第一和第二编程方案之一。 使用选择的编程方案将数据存储在模拟存储器单元的组中。

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