公开(公告)号：US06838374B2

公开(公告)日：2005-01-04

申请号：US10170359

申请日：2002-06-14

申请人： Toshiya Uenishi ,  Satoshi Meguro ,  Masaharu Kubo ,  Masataka Kato ,  Hideo Miura ,  Norio Suzuki

发明人： Toshiya Uenishi ,  Satoshi Meguro ,  Masaharu Kubo ,  Masataka Kato ,  Hideo Miura ,  Norio Suzuki

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L21/4763

CPC分类号： H01L21/76237

摘要： To suppress oxidation of the inner walls of element isolation grooves otherwise occurring during thermal oxidation processes, a nitrogen introducing layer, that has a lower diffusion coefficient relative to an oxidizing agent, is formed at the surface portion of a silicon oxide film buried within an element isolation groove. This nitrogen introduced layer functions as a barrier layer for precluding the oxidizer (such as oxygen, water or the like) in vapor phase from diffusing into the silicon oxide film during thermal processing steps. The nitrogen introduced layer is formed by performing nitrogen ion implantation into the entire surface of a substrate and subsequently applying thermal processing to the substrate to thereby activate the nitrogen that has been doped.

摘要翻译： 为了抑制在热氧化过程中发生的元件隔离槽的内壁的氧化，在埋置在元件内的氧化硅膜的表面部分形成有相对于氧化剂具有较低扩散系数的氮导入层 隔离槽。 该氮引入层用作阻止层，用于排除气相中的氧化剂（例如氧，水等）在热处理步骤期间扩散到氧化硅膜中。 通过在衬底的整个表面中进行氮离子注入并随后对衬底进行热处理从而激活掺杂的氮而形成氮引入层。

公开(公告)号：US06821867B2

公开(公告)日：2004-11-23

申请号：US10421927

申请日：2003-04-24

申请人： Nobuyoshi Matsuura ,  Yasuhiko Kouno ,  Hideo Miura ,  Masaharu Kubo

发明人： Nobuyoshi Matsuura ,  Yasuhiko Kouno ,  Hideo Miura ,  Masaharu Kubo

IPC分类号： H01L2178

CPC分类号： H01L29/7811 ,  H01L23/544 ,  H01L23/562 ,  H01L27/092 ,  H01L29/0657 ,  H01L29/66242 ,  H01L29/66734 ,  H01L29/7371 ,  H01L29/7813 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device and a manufacturing method thereof which can realize fine processing while preventing a warp of a semiconductor wafer. In forming a plurality of semiconductor elements on a semiconductor wafer, grooves for attenuating stress are formed in scribe regions defined between semiconductor element forming regions. Here, the grooves are formed in the scribe regions except for alignment pattern forming regions such that the alignment pattern forming regions remain in the scribe regions. On the alignment pattern forming regions of the scribe regions, an alignment pattern or a TEG pattern which is used in a photolithography step is formed.

摘要翻译： 本发明提供一种能够在防止半导体晶片翘曲的同时实现精细加工的半导体器件及其制造方法。 在半导体晶片上形成多个半导体元件时，在形成半导体元件的区域之间的划线区域形成用于衰减应力的沟槽。 这里，除了对准图案形成区域之外的划线区域中形成凹槽，使得取向图案形成区域保留在划线区域中。 在划线区域的取向图案形成区域中，形成在光刻工序中使用的取向图案或TEG图案。

公开(公告)号：US06630731B2

公开(公告)日：2003-10-07

申请号：US10050951

申请日：2002-01-22

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L25065

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US06492719B2

公开(公告)日：2002-12-10

申请号：US09984089

申请日：2001-10-26

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L25065

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US06381513B1

公开(公告)日：2002-04-30

申请号：US08875183

申请日：1997-07-21

申请人： Satoshi Takase ,  Masaharu Kubo ,  Takeshi Munakata

发明人： Satoshi Takase ,  Masaharu Kubo ,  Takeshi Munakata

IPC分类号： G06F1700

CPC分类号： G07F11/002 ,  G06K17/00 ,  G06Q10/10 ,  G06Q20/123 ,  G06Q20/18 ,  G07F17/0014

摘要： Herein disclosed is an electronic information distributing terminal equipment for storing and distributing the electronic information containing a text information and a corresponding motion image information in a memory card equipped with an electrically reloadable nonvolatile semiconductor memory device, which equipment comprises a card stock having a plurality of memory cards stored in advance with the information which has been transmitted through a communication interface for transmitting the electronic information to be distributed, wherein the electronic information is distributed by discharging the memory card even in response to a demand for distributing only the electronic information, and wherein the memory card inserted with the demand is utilized again as a new card stock. As a result, it is possible to provide an electronic information distributing terminal equipment capable of efficiently conducting the service of distributing the electronic information containing text information and corresponding motion image information.

摘要翻译： 这里公开了一种电子信息分配终端设备，用于在包含电可重新加载的非易失性半导体存储器件的存储卡中存储和分发包含文本信息和相应的运动图像信息的电子信息，该设备包括具有多个 预先存储有通过用于发送要分发的电子信息的通信接口发送的信息的存储卡，其中，即使响应于仅分发电子信息的需求，也通过放电存储卡来分发电子信息，以及 其中插入了需求的存储卡被再次用作新的卡片。 结果，可以提供能够有效地进行分发包含文本信息的电子信息和相应的运动图像信息的服务的电子信息分发终端设备。

公开(公告)号：US06335565B1

公开(公告)日：2002-01-01

申请号：US09319044

申请日：1999-07-30

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L25065

CPC分类号： H01L23/49816 ,  H01L23/49572 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/118 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2224/0401

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US4958320A

公开(公告)日：1990-09-18

申请号：US361633

申请日：1989-06-02

申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： G11C11/411 ,  H01L27/102

CPC分类号： G11C11/4113 ,  G11C11/4116 ,  H01L27/1025

摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。

公开(公告)号：US4514766A

公开(公告)日：1985-04-30

申请号：US482791

申请日：1983-04-07

申请人： Norio Koike ,  Iwao Takemoto ,  Shinya Ohba ,  Toshiaki Masuhara ,  Masaharu Kubo

发明人： Norio Koike ,  Iwao Takemoto ,  Shinya Ohba ,  Toshiaki Masuhara ,  Masaharu Kubo

IPC分类号： H04N5/345 ,  H04N5/372 ,  H04N5/3728 ,  H04N3/15

CPC分类号： H04N3/1575 ,  H01L27/14856 ,  H04N3/1537

摘要： A solid-state imaging device is provided which employs CCDs as vertical shift registers and a horizontal shift register for vertically and horizontally scanning and reading out a large number of photoelectric elements arrayed in a two-dimensional plane. The imaging device is characterized in that the photoelectric elements of each column arranged between the vertical shift registers are alternately connected to the right and left vertical shift registers. This results in the resolution of the device being enhanced sharply.

摘要翻译： 提供了一种使用CCD作为垂直移位寄存器的固态成像装置和用于垂直和水平扫描并读出排列在二维平面中的大量光电元件的水平移位寄存器。 成像装置的特征在于，布置在垂直移位寄存器之间的每列的光电元件交替地连接到左右垂直移位寄存器。 这导致设备的分辨率急剧增加。

公开(公告)号：US4316205A

公开(公告)日：1982-02-16

申请号：US119383

申请日：1980-02-07

申请人： Masakazu Aoki ,  Iwao Takemoto ,  Masaharu Kubo ,  Ryuichi Izawa

发明人： Masakazu Aoki ,  Iwao Takemoto ,  Masaharu Kubo ,  Ryuichi Izawa

IPC分类号： H01L27/146 ,  H01L31/113 ,  H04N5/335 ,  H04N5/374 ,  H01L27/14

CPC分类号： H01L31/1136 ,  H01L27/14643

摘要： In a solid-state imaging device having in one major surface region of a monolithic semiconductor body, photodiodes which are arrayed in two dimensions, vertical switching MOS transistors and horizontal switching MOS transistors which address the photodiodes, MOS transistors which constitute vertical and horizontal scanning circuits for turning "on" and "off" the switching MOS transistors, and MOS transistors which constitute other peripheral circuitry, the photodiodes being constructed of source regions of the vertical switching MOS transistors and the semiconductor body; a solid-state imaging device characterized in that among source and drain regions of the various MOS transistors, the source regions of the vertical switching MOS transistors are lower in the surface impurity concentration and deeper in the junction depth than the other source and drain regions.

摘要翻译： 在具有单片半导体主体的一个主表面区域的固态成像装置中，以二维排列的光电二极管，构成光电二极管的垂直开关MOS晶体管和水平开关MOS晶体管，构成垂直和水平扫描电路的MOS晶体管 为了使开关MOS晶体管“开”和“关”，构成其它外围电路的MOS晶体管，该光电二极管由垂直开关MOS晶体管和半导体本体的源极区构成; 一种固态成像装置，其特征在于，在各种MOS晶体管的源极和漏极区域中，垂直开关MOS晶体管的源极区域的表面杂质浓度较低，并且结深度比其他源极和漏极区域更深。

公开(公告)号：US4301477A

公开(公告)日：1981-11-17

申请号：US120115

申请日：1980-02-11

申请人： Iwao Takemoto ,  Masaharu Kubo ,  Shinya Ohba ,  Shuhei Tanaka ,  Masakazu Aoki

发明人： Iwao Takemoto ,  Masaharu Kubo ,  Shinya Ohba ,  Shuhei Tanaka ,  Masakazu Aoki

IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/365 ,  H04N5/374 ,  H04N5/30 ,  H04N3/14

CPC分类号： H04N5/2173 ,  H01L27/14643 ,  H04N3/1568

摘要： In a solid-state imaging device comprising photodiodes arranged in a two-dimensional array, vertical and horizontal switching MOS transistors for selecting the photodiodes, vertical and horizontal scanning circuits for supplying scanning pulses to the gate electrodes of the vertical and horizontal switching MOS transistors respectively, a signal switching gate MOS transistor is connected between a signal output terminal and a horizontal signal output line connecting in common the horizontal switching MOS transistors.

摘要翻译： 在包括以二维阵列布置的光电二极管的固态成像装置中，用于选择光电二极管的垂直和水平切换MOS晶体管，分别向垂直和水平开关MOS晶体管的栅电极提供扫描脉冲的垂直和水平扫描电路 信号切换栅极MOS晶体管连接在水平开关MOS晶体管共同连接的信号输出端子和水平信号输出线之间。