公开(公告)号：US20050184345A1

公开(公告)日：2005-08-25

申请号：US10655255

申请日：2003-09-04

Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7848 ,  Y10S438/938

Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 沟道区设置在衬底中，并且栅堆叠设置在应变沟道区上方，一对源极/漏极区相对地设置在与沟道区相邻的衬底中，其中源/漏区中的每一个包括晶格 - 错配区域包括具有第二自然晶格常数而不是第一自然晶格常数的第二半导体材料，对应于栅极堆叠的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

公开(公告)号：US20050035369A1

公开(公告)日：2005-02-17

申请号：US10729092

申请日：2003-12-05

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L31/0328

CPC classification number: H01L29/6653 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1104 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A semiconductor device or circuit is formed on a semiconductor substrate with first and second semiconductor materials having different lattice-constants. A first transistor includes a channel region formed oppositely adjacent a source and drain region. At least a portion of the source and drain regions are formed in the second semiconductor material thereby forming lattice-mismatched zones in the first transistor. A second component is coupled to the transistor to form a circuit, e.g., an inverter. The second component can be a second transistor having a conductivity type differing from the first transistor or a resistor.

Abstract translation: 半导体器件或电路在具有不同晶格常数的第一和第二半导体材料的半导体衬底上形成。 第一晶体管包括与源区和漏区相对地形成的沟道区。 源区和漏区的至少一部分形成在第二半导体材料中，从而在第一晶体管中形成晶格失配区。 第二分量耦合到晶体管以形成电路，例如逆变器。 第二部件可以是具有不同于第一晶体管或电阻器的导电类型的第二晶体管。

公开(公告)号：USD420171S

公开(公告)日：2000-02-01

申请号：US99404

申请日：1999-01-20

Applicant: Kurt Alan Fauerbach ,  Chun-Chieh Lin ,  Rachel Clark Stewart

Designer： Kurt Alan Fauerbach ,  Chun-Chieh Lin ,  Rachel Clark Stewart

公开(公告)号：USD418632S

公开(公告)日：2000-01-04

申请号：US99405

申请日：1999-01-20

Applicant: Kurt Alan Fauerbach ,  Chun-Chieh Lin ,  Rachel Clark Stewart

Designer： Kurt Alan Fauerbach ,  Chun-Chieh Lin ,  Rachel Clark Stewart

公开(公告)号：US20170196862A2

公开(公告)日：2017-07-13

申请号：US14876525

申请日：2015-10-06

Applicant: Mark Thomas Miller ,  Corey Anderson ,  Vijayalaksmi Arumugam ,  Brian Richard Bear ,  Hayley Marie Binch ,  Jeremy J. Ciemens ,  Thomas Cleveland ,  Erica Conroy ,  Timothy Richard Coon ,  Bryan A. Frieman ,  Peter Diederik Jan Grootenhuis ,  Raymond Stanley Gross ,  Sara Sabina Hadida-Ruah ,  Haripada Khatuya ,  Pramod Virupax Joshi ,  Paul John Krenitsky ,  Chun-Chieh Lin ,  Gulin Erdogan Marelius ,  Vito Melillo ,  Jason McCartney ,  Georgia McGaughey Nicholls ,  Fabrice Jean Denis Pierre ,  Alina Silina ,  Andreas P. Termin ,  Johnny Uy ,  Jinglan Zhou

Inventor： Mark Thomas Miller ,  Corey Anderson ,  Vijayalaksmi Arumugam ,  Brian Richard Bear ,  Hayley Marie Binch ,  Jeremy J. Ciemens ,  Thomas Cleveland ,  Erica Conroy ,  Timothy Richard Coon ,  Bryan A. Frieman ,  Peter Diederik Jan Grootenhuis ,  Raymond Stanley Gross ,  Sara Sabina Hadida-Ruah ,  Haripada Khatuya ,  Pramod Virupax Joshi ,  Paul John Krenitsky ,  Chun-Chieh Lin ,  Gulin Erdogan Marelius ,  Vito Melillo ,  Jason McCartney ,  Georgia McGaughey Nicholls ,  Fabrice Jean Denis Pierre ,  Alina Silina ,  Andreas P. Termin ,  Johnny Uy ,  Jinglan Zhou

IPC: A61K31/506 ,  A61K31/4418 ,  A61K31/444 ,  A61K31/44 ,  C07D213/84 ,  C07D231/14 ,  A61K31/415 ,  C07D209/42 ,  A61K31/404 ,  C07D401/12 ,  A61K31/4439 ,  C07D401/14 ,  C07D231/12 ,  A61K31/497 ,  C07D417/12 ,  C07D405/14 ,  A61K31/4545 ,  A61K31/4709 ,  A61K31/496 ,  A61K31/4525 ,  A61J1/03 ,  C07D213/82

CPC classification number: A61K31/506 ,  A61J1/035 ,  A61K31/404 ,  A61K31/415 ,  A61K31/44 ,  A61K31/4418 ,  A61K31/4439 ,  A61K31/444 ,  A61K31/4525 ,  A61K31/4545 ,  A61K31/4709 ,  A61K31/496 ,  A61K31/497 ,  C07D209/18 ,  C07D209/42 ,  C07D209/49 ,  C07D213/64 ,  C07D213/73 ,  C07D213/82 ,  C07D213/84 ,  C07D231/12 ,  C07D231/14 ,  C07D231/20 ,  C07D235/24 ,  C07D239/34 ,  C07D401/04 ,  C07D401/12 ,  C07D401/14 ,  C07D403/10 ,  C07D403/12 ,  C07D405/14 ,  C07D407/12 ,  C07D413/14 ,  C07D417/12

Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.

公开(公告)号：US20160240372A9

公开(公告)日：2016-08-18

申请号：US11714416

申请日：2007-03-06

Applicant: Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/76

CPC classification number: H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract translation: 一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分 覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

公开(公告)号：US08569846B2

公开(公告)日：2013-10-29

申请号：US13166481

申请日：2011-06-22

Applicant: Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

Inventor： Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.

Abstract translation: 一种方法包括在半导体衬底上形成栅叠层，并在半导体衬底中形成第一硅锗（SiGe）区，并邻近栅叠。 第一个SiGe区域具有锗与锗和硅的第一原子百分比。 在第一SiGe区域上形成第二SiGe区域。 第二SiGe区域具有锗与锗和硅的第二原子百分比。 第二原子百分比低于第一原子百分比，其中第一和第二SiGe区域形成金属氧化物半导体（MOS）器件的源极/漏极应力源。

公开(公告)号：US20130169168A1

公开(公告)日：2013-07-04

申请号：US13557227

申请日：2012-07-25

Applicant: Chun-Chieh Lin ,  Ming-Han Tsai ,  Chih-Hao Chen

Inventor： Chun-Chieh Lin ,  Ming-Han Tsai ,  Chih-Hao Chen

IPC: G05B19/02 ,  H05B37/02

CPC classification number: G08C17/02

Abstract: A method for controlling grouped devices is disclosed. The method includes receiving a group setting from a group switch on each of the electronic devices, the electronic devices being divided into a plurality of groups according to the group setting of the group switch; a control device emitting a wireless signal comprising group data and operation data to the electronic devices; each of the electronic devices determining whether the group data matches the group setting of the group switch; and if the group data matches the group setting of the group switch, the electronic devices with the group setting matching the group data performing an operation according to the operation data.

Abstract translation: 公开了一种用于控制分组设备的方法。 该方法包括：从每个电子设备上的组交换机接收组设置，电子设备根据组交换机的组设置被划分为多个组; 将包含组数据和操作数据的无线信号发射到电子设备的控制装置; 每个电子设备确定组数据是否与组交换机的组设置相匹配; 并且如果组数据与组交换机的组设置相匹配，则具有与组数据匹配的组的电子设备根据操作数据执行操作。

公开(公告)号：US08324068B2

公开(公告)日：2012-12-04

申请号：US12943487

申请日：2010-11-10

Applicant: Tseung-Yuen Tseng ,  Chun-Chieh Lin ,  Chao-Cheng Lin

Inventor： Tseung-Yuen Tseng ,  Chun-Chieh Lin ,  Chao-Cheng Lin

IPC: H01L21/20

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1625

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Abstract translation: 公开了在基板上形成的非易失性存储器和制造方法。 包含金属层的底部电极设置在基板上。 包含LaNiO3膜的缓冲层设置在金属层上。 包含SrZrO 3膜的电阻层设置在缓冲层上。 顶电极设置在电阻层上。

公开(公告)号：US08062946B2

公开(公告)日：2011-11-22

申请号：US11093847

申请日：2005-03-30

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/336

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract translation: 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，其包含具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。