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82 条记录 (耗时 0.021 秒)

    Electronic assembly and system with vertically connected capacitors
    51.
    发明授权
    Electronic assembly and system with vertically connected capacitors 失效
    具有垂直连接电容器的电子组装和系统

    公开(公告)号：US06713860B2

    公开(公告)日：2004-03-30

    申请号：US09892273

    申请日：2001-06-26

    申请人： Yuan-Liang Li

    发明人： Yuan-Liang Li

    IPC分类号： H01L23053

    CPC分类号： H05K1/185 ,  H01J9/326 ,  H01J61/368 ,  H01J61/86 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10545 ,  H05K2201/10734

    摘要： An electronic assembly includes one or more discrete capacitors (506, 804, 1204), which are vertically connected to a housing, such as an integrated circuit package (1704). Surface mounted capacitors (506) are vertically connected to pads (602) on a top or bottom surface of the package. Embedded capacitors (804, 1204) are vertically connected to vias (808, 816, 1210, and/or 1212) or other conductive structures within the package. Vertically connecting a surface mounted or embedded capacitor involves aligning (1604) side segments (416) of some of the capacitor's terminals with the conductive structures (e.g., pads, vias or other structures) so that the side of the capacitor upon which the side segments reside is substantially parallel with the top or bottom surface of the package. Where a capacitor includes extended terminals (1208), the capacitor can be embedded so that the extended terminals provide additional current shunts through the package.

    摘要翻译： 电子组件包括垂直连接到诸如集成电路封装（1704）的壳体的一个或多个分立电容器（506,804,1204）。 表面安装电容器（506）垂直连接到封装的顶表面或底表面上的焊盘（602）。 嵌入式电容器（804,1204）垂直连接到封装内的通孔（808,816,1210和/或1212）或其他导电结构。 垂直连接表面安装或嵌入式电容器包括使一些电容器端子的侧面区段（416）与导电结构（例如，焊盘，通孔或其他结构）对准（1604），使得电容器的侧面 驻极体基本上平行于包装的顶部或底部表面。 在电容器包括延伸端子（1208）的情况下，可以嵌入电容器，使得延伸端子通过封装件提供额外的电流分路。

    Fiber-free optical interconnect system for chip-to-chip signaling
    52.
    发明授权
    Fiber-free optical interconnect system for chip-to-chip signaling 失效

    公开(公告)号：US06661943B2

    公开(公告)日：2003-12-09

    申请号：US10062795

    申请日：2002-01-30

    申请人： Yuan-Liang Li

    发明人： Yuan-Liang Li

    IPC分类号： G02B642

    CPC分类号： G02B6/43 ,  G02B6/3582 ,  G02B6/3598

    摘要： Embodiments of an apparatus and method for optical chip-to-chip signaling via free-space are disclosed herein. In one representative embodiment of a fiber-free interconnect system in accordance with the teachings of the present invention, a plurality of microchips packages, each including a microchip coupled to a carrier, may be mounted to a surface of a substrate. Each of the plurality of microchip packages may also include at least one optoelectronic microchip coupled to the carrier, and including an optical source and/or an optical detector to generate or detect optical signals, respectively, to facilitate communication between microchips. Each of the plurality of microchip packages may be mounted to the substrate to optically couple the at least one optoelectronic microchip to a corresponding micro-electro mechanical system mirror array to reflect the optical signals to the optical detector, or from the optical source, respectively.

    CAPACITOR HAVING SEPARATE TERMINALS ON THREE OR MORE SIDES AND METHODS OF FABRICATION
    56.
    发明申请
    CAPACITOR HAVING SEPARATE TERMINALS ON THREE OR MORE SIDES AND METHODS OF FABRICATION 审中-公开
    在三面或三面以上具有单独端子的电容器和制造方法

    公开(公告)号：US20060256502A1

    公开(公告)日：2006-11-16

    申请号：US11460290

    申请日：2006-07-27

    申请人： Yuan-Liang Li ,  David Figueroa ,  Chee-Yee Chung

    发明人： Yuan-Liang Li ,  David Figueroa ,  Chee-Yee Chung

    IPC分类号： H01G4/228

    CPC分类号： H01G4/232

    摘要： A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.

    摘要翻译： 多层电容器包括在至少三个侧面上以及多达六个侧面的分开的端子。 根据目标应用，电容器可以以大量不同的配置，类型和尺寸制造。 设置在电容器的不同侧上的单独的端子可以容易地耦合到各种不同的相邻导体，例如模具端子（包括无扰动端子或条），IC封装端子（包括焊盘或条），以及端子 相邻的分立元件。 还描述了制造方法以及将电容器应用于电子组件。

    Capacitor pad network to manage equivalent series resistance
    57.
    发明申请
    Capacitor pad network to manage equivalent series resistance 审中-公开
    电容焊盘网络来管理等效的串联电阻

    公开(公告)号：US20060138639A1

    公开(公告)日：2006-06-29

    申请号：US11024059

    申请日：2004-12-28

    申请人： David Figueroa ,  Jennifer Hester ,  Yuan-Liang Li

    发明人： David Figueroa ,  Jennifer Hester ,  Yuan-Liang Li

    IPC分类号： H01L23/12

    CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/19103 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09627 ,  H05K2201/097 ,  H05K2201/09709

    摘要： According to some embodiments, an apparatus includes a first conductive pad, a first conductive plane, first dielectric material disposed between the first conductive plane and the first conductive pad, a second conductive plane, second dielectric material disposed between the first conductive plane and the second conductive plane, and a first conductive network. The first conductive network includes a first microvia within the first dielectric material and coupled to the first conductive pad, a first conductive trace within the first conductive plane and coupled to the first microvia, a second microvia within the second dielectric material and coupled to the first conductive trace, a second conductive trace within the second conductive plane and coupled to the second microvia, a third microvia within the second dielectric material and coupled to the second conductive trace, a third conductive trace within the first conductive plane and coupled to the third microvia, and a fourth microvia within the second dielectric material and coupled to the third conductive trace.

    摘要翻译： 根据一些实施例，装置包括第一导电焊盘，第一导电平面，设置在第一导电平面和第一导电焊盘之间的第一电介质材料，第二导电平面，第二电介质材料，设置在第一导电平面和第二导电平面之间 导电平面和第一导电网络。 所述第一导电网络包括所述第一电介质材料内的第一微孔并且耦合到所述第一导电焊盘，所述第一导电平面内的第一导电迹线并耦合到所述第一微孔，所述第二介电材料内的第二微孔， 导电迹线，第二导电平面内的第二导电迹线，并且耦合到第二微孔，在第二介电材料内的第三微孔并耦合到第二导电迹线，第一导电平面内的第三导电迹线并耦合到第三微孔 以及在第二电介质材料内的第四微孔并且耦合到第三导电迹线。

    Shunting arrangements to reduce high currents in grid array connectors
    58.
    发明授权
    Shunting arrangements to reduce high currents in grid array connectors 失效
    分流排列以减少电网阵列连接器中的高电流

    公开(公告)号：US06948943B2

    公开(公告)日：2005-09-27

    申请号：US10090796

    申请日：2002-03-06

    申请人： Yuan-Liang Li

    发明人： Yuan-Liang Li

    IPC分类号： H01R31/08 ,  H05K7/10 ,  H05K1/14

    CPC分类号： H01R31/08 ,  H01R12/523 ,  H05K7/1092

    摘要： A shunt connector is provided to electrically couple two electrical components mountable together via a grid array. The connector may provide mechanical support and provides a shunt electrical conduction path to increase current-carrying capacity between the electrical components of the grid array. In an embodiment, at least part of the shunt connector may extend within one of the electrical components so as to provide the shunt electrical conduction path.

    摘要翻译： 提供分流连接器以电耦合通过网格阵列可安装在一起的两个电气部件。 连接器可以提供机械支撑并且提供并联导电路径以增加电网阵列的电气部件之间的载流能力。 在一个实施例中，分流连接器的至少一部分可以在电气部件之一内延伸，以便提供分流导电路径。