公开(公告)号：US4375085A

公开(公告)日：1983-02-22

申请号：US221958

申请日：1981-01-02

申请人： Gary D. Grise ,  Ning Hsieh ,  Howard L. Kalter ,  Chung H. Lam

发明人： Gary D. Grise ,  Ning Hsieh ,  Howard L. Kalter ,  Chung H. Lam

IPC分类号： G11C14/00 ,  G11C11/34 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C16/0433

摘要： This invention provides an improved electrically alterable read only memory system which includes a semiconductor substrate having a diffusion region therein defining one end of a channel region, a control plate, a floating plate separated from the channel region by a thin dielectric layer and disposed between the control plate and the channel region and means for transferring charge to and from the floating plate. A control gate is coupled to the channel region and is located between the diffusion region and the floating plate. The control gate may be connected to a word line and the diffusion region may be connected to a hit/sense line. The channel region is controlled by the word line and the presence or absence of charge on the floating plate. Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate. The charge transfer means includes an enhanced conduction insulator and means for applying appropriate voltages to the control plate and to the control gate to transfer charge to and from the floating plate through the enhanced conduction insulator.

摘要翻译： 本发明提供了一种改进的电可更换只读存储器系统，其包括其中限定通道区域的一端的扩散区域的半导体衬底，控制板，通过薄介电层与沟道区分离的浮置板， 控制板和通道区域以及用于将电荷转移到浮动板和从浮动板传送电荷的装置。 控制栅极耦合到沟道区并且位于扩散区和浮置板之间。 控制栅极可以连接到字线，并且扩散区域可以连接到命中/感测线。 通道区域由字线控制，浮板上有无电荷。 因此，可以通过检测在浮动板下存储在反相电容器中的电荷的存在或不存在来从存储器的单元读取信息。 电荷转移装置包括增强的导电绝缘体和用于向控制板和控制栅极施加适当电压的装置，以通过增强的导电绝缘体将电荷转移到浮动板和从浮动板传输电荷。

公开(公告)号：US09146852B2

公开(公告)日：2015-09-29

申请号：US13610834

申请日：2012-09-11

申请人： Bing Dai ,  Chung H. Lam ,  Jing Li

发明人： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC分类号： G06F12/02

CPC分类号： G06F3/0625 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/5016 ,  G06F12/02 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

摘要翻译： 一种存储系统，包括内存系统和减少内存系统功耗的方法。 存储器系统包括可分配到多个处理器单元之一（例如处理器或处理器核）中的多个存储器单元。 存储器控制器从处理器单元接收对存储器的请求，并从存储器向每个请求处理器单元分配足够的空间。 分配的存储器可以包括存储每个单元的单个位的单个单元（SLC）存储器单元和存储每个单元多于一个位的其它存储器单元。 因此，两个处理器单元可以被分配相同的存储器空间，而一个或更少个分配给另一个的单元的数量。

公开(公告)号：US20140092694A1

公开(公告)日：2014-04-03

申请号：US13584120

申请日：2012-10-28

申请人： Chung H. Lam ,  Jing Li ,  Robert K. Montoye

发明人： Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C7/06 ,  G11C2207/068

摘要： An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.

摘要翻译： 示例性实施例是用于确定存储器单元的二进制值的电路。 该电路包括具有不同电容的并联电容器以选择性地与存储器单元耦合;以及控制器，被配置为将并联电容器迭代地充电至第一电压，直到所选择的并联电容器使第一电压衰减通过存储器单元为第一参考电压 在预定时间范围内，基于所选择的并联电容器确定存储器单元的最高有效位的二进制值，在确定存储器单元的最高有效位的二进制值之后，将所选择的并联电容器充电至第二电压， 并且基于通过存储器单元的所选择的并联电容器处的第二电压的衰减来确定存储器单元的最低有效位的二进制值。

公开(公告)号：US20140052901A1

公开(公告)日：2014-02-20

申请号：US13610834

申请日：2012-09-11

申请人： Bing Dai ,  Chung H. Lam ,  Jing Li

发明人： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC分类号： G06F12/02

CPC分类号： G06F3/0625 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/5016 ,  G06F12/02 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

公开(公告)号：US20140024185A1

公开(公告)日：2014-01-23

申请号：US13551776

申请日：2012-07-18

申请人： Matthew J. BrightSky ,  Chung H. Lam ,  Gen P. Lauer

发明人： Matthew J. BrightSky ,  Chung H. Lam ,  Gen P. Lauer

IPC分类号： H01L21/336

CPC分类号： H01L27/101 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes forming pillars with a doped silicon region on the substrate. An electrically conductive gate material is deposited between and over the pillars. The gate material is etched such that the gate material partially fills a space between the pillars. The pillars are then etched such that a pair of pillars from the pillars include an insulating material over the doped silicon region. A gate contact is deposited between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level, and the insulating material extends below the contact interface level.

摘要翻译： 一种防止栅极接触与衬底上的多个存储器单元的源极接触电连接的方法。 该方法包括在衬底上形成具有掺杂硅区域的柱。 导电栅极材料沉积在支柱之间和之上。 栅极材料被蚀刻，使得栅极材料部分地填充柱之间的空间。 然后蚀刻柱，使得来自柱的一对柱在掺杂硅区域上包括绝缘材料。 栅极接触件沉积在该对柱之间，使得栅极接触件以接触界面水平电耦合栅极材料，并且绝缘材料延伸到接触界面水平以下。

公开(公告)号：US20140022851A1

公开(公告)日：2014-01-23

申请号：US13584423

申请日：2012-08-13

申请人： Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

发明人： Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/004 ,  G11C2213/71 ,  G11C2213/72

摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

公开(公告)号：US08560902B1

公开(公告)日：2013-10-15

申请号：US13587146

申请日：2012-08-16

申请人： Chung H. Lam ,  Jing Li ,  Robert K. Montoye

发明人： Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C15/046 ,  G11C29/32 ,  G11C29/44

摘要： A method for programming a Phase Change Material-Content Addressable Memory (PCM-CAM). The method includes receiving a word to be written in a PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The method further includes repeatedly writing the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and writing the high bits in memory cells of the PCM-CAM only once.

摘要翻译： 一种用于编程相变材料内容可寻址存储器（PCM-CAM）的方法。 该方法包括接收要写入PCM-CAM的单词。 该字包括由PCM-CAM中的低电阻状态表示的低位和由PCM-CAM中的高电阻状态表示的高位。 该方法还包括在PCM-CAM的存储单元中重复写低位，直到存储单元的电阻低于阈值，并将PCM-CAM的存储单元中的高位写入一次。

公开(公告)号：US20130223125A1

公开(公告)日：2013-08-29

申请号：US13407848

申请日：2012-02-29

申请人： John K. DeBrosse ,  Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li

发明人： John K. DeBrosse ,  Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C5/025 ,  G11C8/10 ,  G11C8/14 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0023 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77

摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.

摘要翻译： 一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。 该系统包括列电压。 列电压开关包括列电压和电耦合到双向存取二极管的输出。 列电压包括至少一个写一列电压和至少一个写零列电压。 该系统还包括行电压开关。 行电压开关包括行电压和电耦合到双向存取二极管的输出。 行电压包括至少一个写入一行电压和至少一个写入零行电压。 该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。 该系统包括电耦合到行和列开关的选择线的写入驱动器。

公开(公告)号：US20130163322A1

公开(公告)日：2013-06-27

申请号：US13335310

申请日：2011-12-22

申请人： Chung H. Lam ,  Jing Li

发明人： Chung H. Lam ,  Jing Li

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0092 ,  G11C2211/5622 ,  G11C2213/79

摘要： A system, a method for parallel programming multiple bits of a phase change memory array for high bandwidth. The system and method includes parallel programming scheme wherein a common wordline (WL) is driven with a first pulse of one of: gradually increasing (RESET) or decreasing (SET) amplitudes which control current flow through one or more phase change memory cells associated with the WL. Simultaneously therewith, one or more bitlines (BLs) are driven with one or more second pulses, each second pulse more narrow than that of the first pulse applied to the WL. The starting time of the one or more second pulses may vary with each bitline driven at a time later than, but within the window of the wordline pulse to achieve a programming current suitable for achieving the corresponding memory cell state.

摘要翻译： 一种用于并行编程用于高带宽的相变存储器阵列的多个比特的系统。 该系统和方法包括并行编程方案，其中公共字线（WL）由第一脉冲驱动，第一脉冲是逐渐增加（RESET）或减小（SET）幅度，其控制电流流过与一个或多个相关联的相变存储器单元 WL。 与此同时，一个或多个位线（BL）用一个或多个第二脉冲驱动，每个第二脉冲比施加到WL的第一脉冲的第二脉冲更窄。 一个或多个第二脉冲的开始时间可以随着在比字线脉冲的窗口之外但在窗口内的时间驱动的每个位线而变化，以实现适于实现相应的存储单元状态的编程电流。

公开(公告)号：US20130163321A1

公开(公告)日：2013-06-27

申请号：US13335237

申请日：2011-12-22

申请人： Chung H. Lam ,  Jing Li

发明人： Chung H. Lam ,  Jing Li

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/00 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0057 ,  G11C2013/0076 ,  G11C2013/0092

摘要： An RC-based sensing scheme to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing scheme ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing scheme is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing scheme is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift.

摘要翻译： 一种基于RC的感测方案，可有效检测编程的相变材料（PCM）存储单元的单元电阻。 感测方案确保每个单元的相同物理配置（编程后）：相同的无定形体积，相同的阱密度/分布等。感测方案基于度量：基于RC的感测放大器实现两个触发点。 将这两个点之间的测量时间间隔用作度量以确定编程的单元状态（例如电阻）是否被编程为期望值。 基于RC的感测方案被嵌入到迭代PCM单元编程技术中，以确保在编程之后每个级别的电阻分布紧密; 并确保层次混叠的概率非常小，导致较少的有问题的漂移。