公开(公告)号：US09947804B1

公开(公告)日：2018-04-17

申请号：US15657659

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Steven Bentley

IPC: H01L21/84 ,  H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/78696 ,  H01L21/823412 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66431 ,  H01L29/775 ,  H01L29/778

Abstract: An IC structure according to the disclosure includes: a substrate; a pair of transistor sites positioned on the substrate, wherein an upper surface of the substrate laterally between the pair of transistor sites defines a separation region; a pair of nanosheet stacks, each positioned on one of the pair of transistor sites; an insulative liner conformally positioned on the upper surface of the substrate within the separation region, and a sidewall surface of each of the pair of transistor sites; a semiconductor mandrel positioned on the insulative liner and over the separation region; a pair of insulator regions each positioned laterally between the semiconductor mandrel and the insulative liner on the sidewall surfaces of each of the pair of transistor sites; and a source/drain epitaxial region positioned over the pair of insulator regions and the semiconductor mandrel, wherein the source/drain epitaxial region laterally abuts the pair of nanosheet stacks.

公开(公告)号：US20180061832A1

公开(公告)日：2018-03-01

申请号：US15801023

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US09875940B2

公开(公告)日：2018-01-23

申请号：US14820701

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/02181 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

公开(公告)号：US09831132B2

公开(公告)日：2017-11-28

申请号：US15645395

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US09824920B2

公开(公告)日：2017-11-21

申请号：US15089834

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is formed in the first plurality of gate cavities. A first conductive material is formed in at least a subset of the first plurality of gate cavities above the work function material layer to define a first plurality of gate structures. A first contact recess is formed in the first dielectric layer between two of the first plurality of gate structures. A second conductive material is formed in the first contact recess. The work function material layer is recessed selectively to the first and second conductive materials to define a plurality of cap recesses. A cap layer is formed in the plurality of cap recesses.

公开(公告)号：US09761495B1

公开(公告)日：2017-09-12

申请号：US15050540

申请日：2016-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.

公开(公告)号：US09735060B1

公开(公告)日：2017-08-15

申请号：US15006304

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L21/302 ,  H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/823481

Abstract: For an integrated circuit product comprising a non-tapered FinFET device formed in a first region of the substrate and a tapered FinFET device in a second region of the substrate, the method includes, among other things, forming the fins for the non-tapered FinFET device in the first region by performing a fin-cut-last process and forming the fins for the tapered FinFET by performing a fin-cut-first process.

公开(公告)号：US20170213767A1

公开(公告)日：2017-07-27

申请号：US15006304

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/823481

Abstract: For an integrated circuit product comprising a non-tapered FinFET device formed in a first region of the substrate and a tapered FinFET device in a second region of the substrate, the method includes, among other things, forming the fins for the non-tapered FinFET device in the first region by performing a fin-cut-last process and forming the fins for the tapered FinFET by performing a fin-cut-first process.

公开(公告)号：US09634115B2

公开(公告)日：2017-04-25

申请号：US14301864

申请日：2014-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Xiuyu Cai

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L29/4232 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer.

公开(公告)号：US09583584B2

公开(公告)日：2017-02-28

申请号：US14795984

申请日：2015-07-10

Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

Inventor： Chanro Park ,  Injo Ok

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/66 ,  H01L21/82

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/70 ,  H01L21/82 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/66545

Abstract: Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Abstract translation: 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。