公开(公告)号：US20200091143A1

公开(公告)日：2020-03-19

申请号：US16134173

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE ,  Laertis ECONOMIKOS

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.

公开(公告)号：US20200035543A1

公开(公告)日：2020-01-30

申请号：US16047078

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Haiting WANG ,  Hong YU ,  Laertis ECONOMIKOS

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

公开(公告)号：US20190378763A1

公开(公告)日：2019-12-12

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Ruilong XIE ,  Shesh Mani PANDEY ,  Hui ZANG ,  Garo Jacques DERDERIAN ,  Scott BEASOR

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US20190355838A1

公开(公告)日：2019-11-21

申请号：US15980436

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Ruilong XIE ,  Scott BEASOR

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28

Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an α-Si layer in a recess over the epi S/D; forming an oxide layer over the α-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and α-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.

公开(公告)号：US20190221650A1

公开(公告)日：2019-07-18

申请号：US15873565

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Guowei XU ,  Keith TABAKMAN ,  Viraj SARDESAI

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/28

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.

公开(公告)号：US20190115426A1

公开(公告)日：2019-04-18

申请号：US15786284

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Hui ZANG ,  Xusheng WU

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

公开(公告)号：US20180331212A1

公开(公告)日：2018-11-15

申请号：US15592444

申请日：2017-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Josef WATTS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/7827 ,  H01L29/4966 ,  H01L29/66666

Abstract: A semiconductor structure includes a substrate and a vertical FinFET disposed over the substrate. The vertical FinFET includes: a bottom source/drain (S/D) region disposed over the substrate, a fin extending vertically upwards from the bottom S/D region, the fin having a first (1st) sidewall, a second (2nd) sidewall and a top portion, an upper S/D region disposed over the top portion of the fin, the fin defining a channel between the bottom S/D region and the upper S/D region, a 1st gate structure having a 1st metal gate, the 1st gate structure disposed on the 1st sidewall of the fin, and a 2nd gate structure having a 2nd metal gate, the 2nd gate structure disposed on the 2nd sidewall of the fin. The 1st and 2nd metal gates are electrically isolated from each other by the fin.

公开(公告)号：US20170338247A1

公开(公告)日：2017-11-23

申请号：US15160623

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER ,  Min-hwa CHI

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L27/11

CPC classification number: H01L27/1207 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/4966

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.

公开(公告)号：US20170338156A1

公开(公告)日：2017-11-23

申请号：US15156767

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI ,  Jinping LIU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

公开(公告)号：US20170309563A1

公开(公告)日：2017-10-26

申请号：US15137362

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/60

Abstract: A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a first electrode a dielectric of the capacitor, and, depositing a metal within said capacitor trench and said interconnection trench wherein the metal forms a second electrode of the capacitor and also forms an interconnection between layers of an interconnecting structure of a semiconductor device. A semiconductor structure, comprising a dual damascene structure having a capacitor trench for a capacitor, the capacitor including a first electrode, a second electrode, and a high-K dielectric between the first and second electrodes, the high-k dielectric configured to seal the first electrode from the second electrode and from subsequent wiring layers of the interconnecting structure of the semiconductor device, and, an interconnection trench for a metal interconnection to form an interconnection between the interconnecting structure of the semiconductor device.