公开(公告)号：US20100035379A1

公开(公告)日：2010-02-11

申请号：US12535713

申请日：2009-08-05

申请人： Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Yasuo NAKAMURA

发明人： Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Yasuo NAKAMURA

IPC分类号： H01L29/24

CPC分类号： H01L29/78696 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/32139 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/263 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

摘要： To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

摘要翻译： 为了提供一种以少数步骤制造包括具有优异电特性和高可靠性的薄膜晶体管的半导体器件的方法。 在包含In，Ga和Zn的氧化物半导体膜上形成沟道保护层之后，形成具有n型导电性的膜和导电膜，并且在导电膜上形成抗蚀剂掩模。 使用沟道保护层和栅极绝缘膜作为具有抗蚀剂掩模的蚀刻阻挡层来蚀刻导电膜，具有n型导电性的膜和包含In，Ga和Zn的氧化物半导体膜，使得源极和漏极层 ，缓冲层和半导体层。

公开(公告)号：US20100032668A1

公开(公告)日：2010-02-11

申请号：US12535715

申请日：2009-08-05

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L29/786 ,  H01L21/34

CPC分类号： H01L29/66742 ,  H01L29/78621 ,  H01L29/7869

摘要： An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

摘要翻译： 一个实施例是包括交错（顶栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 层。 有意地提供具有比半导体层更高的载流子浓度的金属氧化物层作为源极和漏极电极层与半导体层之间的缓冲层，从而形成欧姆接触。

公开(公告)号：US20100025678A1

公开(公告)日：2010-02-04

申请号：US12511285

申请日：2009-07-29

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L29/786 ,  H01L29/22 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/7869

摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

摘要翻译： 本发明的目的是提供一种包括具有良好的电性能和高可靠性的薄膜晶体管的半导体器件，以及一种以高生产率制造半导体器件的方法。 在倒置交错（底栅极）薄膜晶体管中，使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且在半导体层和源之间设置使用金属氧化物层形成的缓冲层， 漏电极层。 有意地提供金属氧化物层作为半导体层与源极和漏极电极层之间的缓冲层，从而获得欧姆接触。

公开(公告)号：US20100025675A1

公开(公告)日：2010-02-04

申请号：US12511247

申请日：2009-07-29

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L29/26 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/016 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/15 ,  H01L27/3225 ,  H01L27/3241 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78618

摘要： In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.

摘要翻译： 在有源矩阵显示装置中，包括在电路中的薄膜晶体管的电特性是重要的，显示装置的性能取决于电特性。 因此，通过使用包括In，Ga和Zn的氧化物半导体膜用于反向交错薄膜晶体管，可以减小薄膜晶体管的电特性的变化。 通过溅射法连续地形成三层栅极绝缘膜，氧化物半导体层和沟道保护层，而不暴露于空气。 此外，在氧化物半导体层中，与沟道保护膜重叠的区域的厚度大于与导电膜接触的区域的厚度。

公开(公告)号：US20090321737A1

公开(公告)日：2009-12-31

申请号：US12490447

申请日：2009-06-24

申请人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI ,  Takuya HIROHASHI

发明人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI ,  Takuya HIROHASHI

IPC分类号： H01L29/04

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

摘要翻译： 至少在源区和漏区侧，薄膜晶体管包括作为缓冲层的半导体层，该半导体层含有氮并且包括在栅极绝缘层和源极和漏极区之间的非晶结构中的晶体区域。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比，可以提高薄膜晶体管的导通电流。 此外，与在沟道形成区域中包含微晶半导体的薄膜晶体管相比，可以减小薄膜晶体管的截止电流。

公开(公告)号：US20090261328A1

公开(公告)日：2009-10-22

申请号：US12423123

申请日：2009-04-14

申请人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

发明人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/4404 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in a state that a plurality of crystalline particles is dispersed in an amorphous silicon and that the crystalline particles have an inverted conical or inverted pyramidal shape. The crystalline particles grow approximately radially in a direction in which the semiconductor layer is deposited. Vertexes of the inverted conical or inverted pyramidal crystal particles are located apart from an interface between the gate insulating layer and the semiconductor layer.

摘要翻译： 公开了一种薄膜晶体管，其在具有绝缘表面的衬底上方包括覆盖栅电极的栅绝缘层; 用作沟道形成区域的半导体层; 以及包含赋予一种导电型的杂质元素的半导体层。 半导体层以多个结晶粒子分散在非晶硅中的状态存在，并且结晶粒子具有倒锥形或倒棱锥形状。 晶体颗粒沿半导体层沉积的方向大致径向生长。 倒锥形或倒锥形晶体颗粒的顶点位于与栅极绝缘层和半导体层之间的界面之外。

公开(公告)号：US20090218568A1

公开(公告)日：2009-09-03

申请号：US12391398

申请日：2009-02-24

申请人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US20120299074A1

公开(公告)日：2012-11-29

申请号：US13477334

申请日：2012-05-22

申请人： Atsushi HIROSE ,  Hidekazu MIYAIRI ,  Yoshitaka YAMAMOTO ,  Tomohiro KIMURA

发明人： Atsushi HIROSE ,  Hidekazu MIYAIRI ,  Yoshitaka YAMAMOTO ,  Tomohiro KIMURA

IPC分类号： H01L27/06

CPC分类号： H01L29/78633 ,  H01L29/78648

摘要： A semiconductor device in which light leakage due to misalignment is prevented even when a black matrix layer is not expanded to a designed value or more is provided. In a semiconductor device including a dual-gate thin film transistor in which a semiconductor layer is sandwiched between a bottom gate electrode and a top gate electrode, the top gate electrode is formed of a first black matrix layer, and the top gate electrode overlaps with the semiconductor layer.

摘要翻译： 即使黑矩阵层不扩展到设计值以上，也能够防止由于未对准而导致的漏光的半导体装置。 在包括半导体层夹在底栅电极和顶栅电极之间的双栅极薄膜晶体管的半导体器件中，顶栅电极由第一黑矩阵层形成，顶栅电极与 半导体层。

公开(公告)号：US20120273779A1

公开(公告)日：2012-11-01

申请号：US13546345

申请日：2012-07-11

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/016 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/15 ,  H01L27/3225 ,  H01L27/3241 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78618

摘要： In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.

摘要翻译： 在有源矩阵显示装置中，包括在电路中的薄膜晶体管的电特性是重要的，显示装置的性能取决于电特性。 因此，通过使用包括In，Ga和Zn的氧化物半导体膜用于反向交错薄膜晶体管，可以减小薄膜晶体管的电特性的变化。 通过溅射法连续地形成三层栅极绝缘膜，氧化物半导体层和沟道保护层，而不暴露于空气。 此外，在氧化物半导体层中，与沟道保护膜重叠的区域的厚度大于与导电膜接触的区域的厚度。

公开(公告)号：US20120108006A1

公开(公告)日：2012-05-03

申请号：US13346118

申请日：2012-01-09

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L21/36

CPC分类号： H01L29/66969 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/7869

摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.