公开(公告)号：US12057364B2

公开(公告)日：2024-08-06

申请号：US17991503

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3192 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L23/3128 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/95001

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US20230317705A1

公开(公告)日：2023-10-05

申请号：US17707366

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Bernd Waidhas ,  Georg Seidemann ,  Stephan Stoeckl ,  Pouya Talebbeydokhti ,  Stefan Reif ,  Eduardo De Mesa ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/18 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/181 ,  H01L2225/06572 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1094 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

公开(公告)号：US20230317562A1

公开(公告)日：2023-10-05

申请号：US17708968

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Jan Proschwitz ,  Stefan Reif ,  Vishnu Prasad ,  Georg Seidemann

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/03 ,  H01L24/81 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/06515 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/0231

Abstract: A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.

公开(公告)号：US11581287B2

公开(公告)日：2023-02-14

申请号：US16024700

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Sanka Ganesan ,  Bernd Waidhas ,  Thomas Wagner ,  Lizabeth Keser

IPC: H01L25/065

Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

公开(公告)号：US11456116B2

公开(公告)日：2022-09-27

申请号：US16474015

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Bernd Waidhas ,  Sonja Koller ,  Reinhard Mahnkopf ,  Georg Seidemann

IPC: H01F27/24 ,  H01F41/04 ,  H01F17/00 ,  H01L23/64 ,  H01L27/01 ,  H01L49/02

Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.

公开(公告)号：US11134573B2

公开(公告)日：2021-09-28

申请号：US16642801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US11127813B2

公开(公告)日：2021-09-21

申请号：US16617548

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin

IPC: H01L23/00 ,  H01L21/00 ,  H01L49/02 ,  H01F17/04 ,  H01L21/02 ,  H01L21/56 ,  H01L23/64

Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.

公开(公告)号：US20200352035A1

公开(公告)日：2020-11-05

申请号：US16642801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-rid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US09904321B2

公开(公告)日：2018-02-27

申请号：US14778070

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Dirk Plenkers ,  Hans-Joachim Barth ,  Bernd Waidhas ,  Yen Hsiang Chew ,  Kooi Chi Ooi ,  Howe Yin Loo

IPC: G06F1/16 ,  B29C39/02 ,  B29C39/10 ,  B29C65/48 ,  G02C5/14 ,  G02C11/00 ,  B29L31/34

CPC classification number: G06F1/163 ,  B29C39/021 ,  B29C39/10 ,  B29C65/4825 ,  B29L2031/3481 ,  G02C5/143 ,  G02C11/10

Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.