公开(公告)号：US20200321435A1

公开(公告)日：2020-10-08

申请号：US16303654

申请日：2016-06-17

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/02 ,  H01L29/66

Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

公开(公告)号：US10770593B2

公开(公告)日：2020-09-08

申请号：US16081572

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Tahir Ghani ,  Willy Rachmady ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Anand S. Murthy ,  Chandra S. Mohapatra

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

Abstract: Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.

公开(公告)号：US10734412B2

公开(公告)日：2020-08-04

申请号：US16306295

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Chandra S. Mohapatra ,  Mauro J. Kobrinsky ,  Patrick Morrow

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06

Abstract: Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material. Other embodiments may be described and/or disclosed.

公开(公告)号：US10580865B2

公开(公告)日：2020-03-03

申请号：US15776996

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Nadia M. Rahhal-Orabi ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L29/78

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US10516021B2

公开(公告)日：2019-12-24

申请号：US15777553

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Karthik Jambunathan ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Seiyon Kim ,  Jun Sung Kang

IPC: H01L29/10 ,  H01L29/161 ,  H01L29/06 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78

Abstract: Techniques are disclosed for fabricating semiconductor transistor devices configured with a sub-fin insulation layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with a transistor). The parasitic leakage is reduced by fabricating transistors with a sacrificial layer in a sub-fin region of the substrate below at least a channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced, either in whole or in part, with a dielectric material. The dielectric material increases the electrical resistivity of the substrate between corresponding source and drain portions of the fin, thus reducing parasitic leakage.

公开(公告)号：US20190221649A1

公开(公告)日：2019-07-18

申请号：US16327198

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Karthik Jambunathan ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Patrick Morrow ,  Mauro J. Kobrinsky

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L27/088 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/41766 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/7851

Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

公开(公告)号：US20190198658A1

公开(公告)日：2019-06-27

申请号：US16327206

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Willy Rachmady ,  Anand S. Murthy ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/26 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8252 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/26 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.

公开(公告)号：US10290709B2

公开(公告)日：2019-05-14

申请号：US15504280

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/762 ,  H01L29/04

Abstract: Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.

公开(公告)号：US10243078B2

公开(公告)日：2019-03-26

申请号：US15525164

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Willy Rachmady ,  Tahir Ghani ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass

IPC: H01L29/78 ,  H01L29/26 ,  H01L29/66 ,  H01L29/778 ,  H01L29/267

Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

公开(公告)号：US20190035889A1

公开(公告)日：2019-01-31

申请号：US16071894

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L21/764 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/0243 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30612 ,  H01L21/30625 ,  H01L21/3245 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels.