公开(公告)号：US20180151732A1

公开(公告)日：2018-05-31

申请号：US15575008

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  ANAND S. MURTHY ,  TAHIR GHANI ,  GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  SEAN T. MA ,  CORY E. WEBER

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are disclosed for resistance reduction in p-MOS transistors having epitaxially grown boron-doped silicon germanium (SiGe:B) S/D regions. The techniques can include growing one or more interface layers between a silicon (Si) channel region of the transistor and the SiGe:B replacement S/D regions. The one or more interface layers may include: a single layer of boron-doped Si (Si:B); a single layer of SiGe:B, where the Ge content in the interface layer is less than that in the resulting SiGe:B S/D regions; a graded layer of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage; or multiple stepped layers of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage at each step. Inclusion of the interface layer(s) reduces resistance for on-state current flow.

公开(公告)号：US20180145174A1

公开(公告)日：2018-05-24

申请号：US15860292

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  B82Y10/00 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US20170012124A1

公开(公告)日：2017-01-12

申请号：US15116453

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/092

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

Abstract translation: 公开了用于改善锗（Ge）富集的p-MOS源极/漏极触点的集成的技术，例如降低接触电阻。 这些技术包括将p型富锗层直接沉积在接触沟槽位置的硅（Si）表面上，因为Si表面有利于沉积高质量的导电富Ge材料。 在一个示例性方法中，在去除先前沉积在源极/漏极位置中的牺牲硅锗（SiGe）层之后，在源/漏接触沟槽位置中的富Si层沉积在Si衬底的表面上。 在另一示例性方法中，富集层沉积在接触沟槽位置的Si包覆层上，其中Si包覆层沉积在功能性p型SiGe层上。 在一些情况下，富锗层包含至少50％的Ge（并且可以含有锡（Sn）和/或Si），并且是以高于1E20cm-3的掺杂的硼（B）。

公开(公告)号：US20160372547A1

公开(公告)日：2016-12-22

申请号：US15255902

申请日：2016-09-02

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY

IPC: H01L29/06 ,  H01L23/535 ,  H01L29/36 ,  H01L29/417

CPC classification number: H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Abstract translation: 公开了用于形成具有高浓度锗的源/漏区的列IV晶体管器件的技术，并且相对于常规器件显示降低的寄生电阻。 在一些示例性实施例中，源极/漏极区域各自包括薄的p型硅或锗或SiGe沉积，源/漏材料的其余部分沉积为p型锗或锗合金（例如锗：锡或其他 合适的应变诱导剂，并且锗含量为至少80原子％和20原子％以下的其他组分）。 在某些情况下，可以在富锗盖层中观察到应变松弛的证据，包括失配位错和/或穿透位错和/或双胞胎。 可以使用多个晶体管配置，包括平面和非平面晶体管结构（例如，FinFET和纳米线晶体管），以及应变和非限制的通道结构。

公开(公告)号：US20160260802A1

公开(公告)日：2016-09-08

申请号：US15155806

申请日：2016-05-16

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KELIN J. KUHN ,  SEIYON KIM ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0676 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7855 ,  H01L29/78696

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20160240534A1

公开(公告)日：2016-08-18

申请号：US15024258

申请日：2013-12-18

Applicant: INTEL CORPORATION

Inventor： ANAND S. MURTHY ,  NICK LINDERT ,  GLENN A. GLASS

IPC: H01L27/092 ,  H01L21/265 ,  H01L29/40 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/26506 ,  H01L21/3065 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78696

Abstract: Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (Leff) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (Xud) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (Leff) and improves the control that the gate has over the channel.

Abstract translation: 公开了通过在沟道与源极和漏极区的界面处沉积栅极控制层（GCL）来增加有效电栅极长度（Leff）来改善晶体管的沟道上的栅极控制的技术。 GCL是在使用替换S / D沉积形成晶体管时可以沉积的名义上未掺杂的层（或相对于重掺杂的S / D填充材料的基本上较低的掺杂层）。 在形成这种空穴之后并且沉积重掺杂的S / D填充材料之前，可以将GCL选择性地沉积在S / D腔中。 以这种方式，GCL通过栅极堆叠减少源极和漏极底层（Xud），并进一步分离重掺杂的源极和漏极区域。 这又增加了有效电门长度（Leff），并且改善了栅极通过通道的控制。

公开(公告)号：US20160163802A1

公开(公告)日：2016-06-09

申请号：US14906713

申请日：2013-08-23

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY

IPC: H01L29/205 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02241 ,  H01L21/02247 ,  H01L21/02373 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76264 ,  H01L27/0255 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems.

Abstract translation: 公开了在用于诸如金属氧化物半导体（MOS）晶体管的半导体器件的III-V沟道层和IV族衬底之间使用高电阻层的技术。 可以使用高电阻层来最小化（或消除）电流从源极到漏极的流动，其不同于直接通过通道的路径。 在一些情况下，高电阻层可以是III-V宽带隙层。 在一些这种情况下，宽带隙层可具有大于1.4电子伏（eV）的带隙，并且甚至可以具有大于2.0eV的带隙。 在其他情况下，例如，宽带隙层可以通过氧化或氮化部分或完全转变为绝缘体。 所得到的结构可以与平面，翅片或纳米线/纳米级晶体管架构一起使用以帮助防止衬底泄漏问题。

公开(公告)号：US20150206942A1

公开(公告)日：2015-07-23

申请号：US14673143

申请日：2015-03-30

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract translation: 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用例如硅或硅锗（SiGe）源极/漏极区域上的一系列金属的标准接触堆叠来实现。 根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂锗层以显着降低接触电阻。 根据本公开，包括平面和非平面晶体管结构（例如，FinFET）以及应变和非限制的通道结构，许多晶体管配置和合适的制造工艺将是显而易见的。 分级缓冲可用于减少错配错位。 这些技术特别适用于实现p型器件，但如果需要，可以用于n型器件。