公开(公告)号：US20240063100A1

公开(公告)日：2024-02-22

申请号：US17889229

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Mohammad Mamunur RAHMAN ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Kemal AYGÜN ,  Cemil GEYIK

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/49811

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.

公开(公告)号：US20230420357A1

公开(公告)日：2023-12-28

申请号：US17848624

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Sameer PAITAL

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/0217 ,  H01L21/486 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.

公开(公告)号：US20230405976A1

公开(公告)日：2023-12-21

申请号：US18241067

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Patrick QUACH ,  Dilan SENEVIRATNE

IPC: B32B17/10 ,  B32B15/20 ,  H01L23/00 ,  H01L23/48

CPC classification number: B32B17/10192 ,  B32B15/20 ,  H01L24/09 ,  H01L23/481 ,  H01L2224/02379

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

公开(公告)号：US20230317653A1

公开(公告)日：2023-10-05

申请号：US17709367

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Xiaoxuan SUN ,  Amey Anant APTE ,  Dingying David XU ,  Sairam AGRAHARAM ,  Gang DUAN ,  Ashay DANI

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/80379 ,  H01L2224/8049 ,  H01L2924/07025 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/13025 ,  H01L24/13 ,  H01L24/03 ,  H01L2224/03845 ,  H01L2224/94 ,  H01L24/94 ,  H01L2224/80855 ,  H01L2224/80201 ,  H01L2225/1023 ,  H01L2225/1047

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.

公开(公告)号：US20220254721A1

公开(公告)日：2022-08-11

申请号：US17732365

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20220238458A1

公开(公告)日：2022-07-28

申请号：US17716947

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20210343673A1

公开(公告)日：2021-11-04

申请号：US17366469

申请日：2021-07-02

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

IPC: H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20210125912A1

公开(公告)日：2021-04-29

申请号：US16666202

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG ,  Brandon C. MARIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US20210050289A1

公开(公告)日：2021-02-18

申请号：US16539254

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Srinivas PIETAMBARAM ,  Gang DUAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64

Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.

公开(公告)号：US20210014972A1

公开(公告)日：2021-01-14

申请号：US16505403

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Tarek IBRAHIM ,  Srinivas PIETAMBARAM ,  Andrew J. BROWN ,  Gang DUAN ,  Jeremy ECTON ,  Sheng C. LI

IPC: H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K1/11 ,  H05K3/40 ,  H05K3/28

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.