公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20230317653A1

公开(公告)日：2023-10-05

申请号：US17709367

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Xiaoxuan SUN ,  Amey Anant APTE ,  Dingying David XU ,  Sairam AGRAHARAM ,  Gang DUAN ,  Ashay DANI

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/80379 ,  H01L2224/8049 ,  H01L2924/07025 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/13025 ,  H01L24/13 ,  H01L24/03 ,  H01L2224/03845 ,  H01L2224/94 ,  H01L24/94 ,  H01L2224/80855 ,  H01L2224/80201 ,  H01L2225/1023 ,  H01L2225/1047

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.

公开(公告)号：US20250106983A1

公开(公告)日：2025-03-27

申请号：US18373457

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Kyle ARRINGTON ,  Dingying David XU ,  Ziyin LIN ,  Timothy GOSSELIN ,  Elah BOZORG-GRAYELI ,  Aravindha ANTONISWAMY ,  Wei LI ,  Haobo CHEN ,  Yiqun BAI ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Ashay DANI

IPC: H05K1/02 ,  H05K1/03

Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.