公开(公告)号：US09991258B2

公开(公告)日：2018-06-05

申请号：US15292768

申请日：2016-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.

公开(公告)号：US09728419B2

公开(公告)日：2017-08-08

申请号：US14697306

申请日：2015-04-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/3086 ,  H01L21/0338 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/32136 ,  H01L29/66545 ,  H01L29/66795

Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.

公开(公告)号：US20170186747A1

公开(公告)日：2017-06-29

申请号：US14982438

申请日：2015-12-29

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  He Hong ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/7848

Abstract: A method includes forming a semiconductor fin on a semiconductor substrate; depositing a cladding layer on a portion of the semiconductor fin, wherein the cladding layer comprises a metalloid; annealing the semiconductor substrate to oxidize the cladding layer such that ions are condensed therefrom and are diffused into the semiconductor fin while the cladding layer is converted to an oxide layer; and removing the oxide layer to expose the semiconductor fin having a diffused fin portion comprising greater than or equal to 55% of the metalloid.

公开(公告)号：US09508713B2

公开(公告)日：2016-11-29

申请号：US14198005

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/16 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

Abstract translation: 一种形成鳍状场效应晶体管器件的方法包括在衬底上形成包括硅的一个或多个第一鳍片，在一个或多个第一鳍片的侧面上形成外延层，以及去除一个或多个第一鳍片以形成 多个第二鳍片。

公开(公告)号：US20160329214A1

公开(公告)日：2016-11-10

申请号：US15212972

申请日：2016-07-18

Applicant: International Business Machines Corporation

Inventor： Chiahsun Tseng ,  David V. Horak ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/3081 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/67063 ,  Y10T428/24802

Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.

Abstract translation: 金属层沉积在下层材料层上。 金属层包括可通过等离子体氧化和/或氮化转化为含介电金属的化合物的元素金属。 在金属层上形成硬掩模部分。 进行等离子体氧化或氮化以将金属层的物理暴露表面转化为含介电金属的化合物。 重复将硬掩模部分的表面拉回序列，沟槽蚀刻，另一表面拉回和将顶表面转化为含介电金属的化合物，以形成具有不受光刻最小值限制的间隔的线图案 尺寸。

公开(公告)号：US20160035650A1

公开(公告)日：2016-02-04

申请号：US14884076

申请日：2015-10-15

Applicant: International Business Machines Corporation

Inventor： Chiahsun Tseng ,  Jin Liu ,  Lei Zhuang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

公开(公告)号：US20150357328A1

公开(公告)日：2015-12-10

申请号：US14828551

申请日：2015-08-18

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Chiahsun Tseng ,  Chun-Chen Yeh

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653

Abstract: The present invention relates generally to semiconductor devices, and particularly to fabricating a shallow trench isolation (STI) region in fin field effect transistors (FinFETs) having a small fin pitch. A structure is disclosed. The structure may include: a semiconductor substrate; a plurality of fins on the semiconductor substrate; a plurality of caps on the fins; an isolation layer on the semiconductor substrate and between the plurality of fins, the isolation layer having an upper surface that is substantially flush with an upper surface of the plurality of caps; an isolation trench in the semiconductor substrate; a fin trench where one of the plurality of fins and one of the plurality of caps have been removed; and insulating material in the isolation trench and the fin trench to form an isolation region, the isolation region having an upper surface that is substantially flush with the upper surface of the isolation layer.

Abstract translation: 本发明一般涉及半导体器件，特别涉及制造鳍片间距小的鳍式场效应晶体管（FinFET）中的浅沟槽隔离（STI）区域。 公开了一种结构。 该结构可以包括：半导体衬底; 半导体衬底上的多个散热片; 翅片上的多个帽; 在所述半导体衬底上和所述多个鳍之间的隔离层，所述隔离层具有与所述多个帽的上表面基本齐平的上表面; 半导体衬底中的隔离沟槽; 其中所述多个翅片中的一个和所述多个帽中的一个已经被去除的翅片沟槽; 以及隔离沟槽和散热片沟槽中的绝缘材料以形成隔离区域，所述隔离区域具有与隔离层的上表面基本齐平的上表面。

公开(公告)号：US20150255300A1

公开(公告)日：2015-09-10

申请号：US14198005

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/308 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

Abstract translation: 一种形成鳍状场效应晶体管器件的方法包括在衬底上形成包括硅的一个或多个第一鳍片，在一个或多个第一鳍片的侧面上形成外延层，以及去除一个或多个第一鳍片以形成 多个第二鳍片。

公开(公告)号：US20150243760A1

公开(公告)日：2015-08-27

申请号：US14191751

申请日：2014-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

Abstract translation: 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。

公开(公告)号：US09093326B2

公开(公告)日：2015-07-28

申请号：US14058341

申请日：2013-10-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831

Abstract: A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein.

Abstract translation: 通过外延在半导体材料层上形成硅锗合金层。 在硅锗合金层上形成不透氧层。 对不透氧层和硅锗合金层进行图案化以形成硅锗合金翅片和不透氧盖的叠层。 通过沉积，平坦化和凹陷形成浅沟槽隔离结构或透氧介电材料。 在硅锗合金翅片和不透氧盖的每个堆叠周围形成不透氧隔离物。 进行热氧化处理以将每个硅锗合金翅片的下部转换成硅氧化锗。 在热氧化过程中，锗原子扩散到硅锗合金翅片的未氧化部分，以增加其中的锗浓度。